FPGA Implementation of an Emulator for Wireless Sensor Node with Pt100 Temperature Sensor Uzma Quadri 1 Dept of Electronics Engineering, G.H.Raisoni College of Engineering, Nagpur, India quadri.uzma@gmail.com Pankaj Rangaree 2 Dept of Electronics Engineering, G.H.Raisoni College of Engineering, Nagpur, India pankajrangaree12@rediffmail.com Dr.Gajendra M. Asutkar 3 Dept of Electronics & Communication Engineering, P.I.E.T Nagpur, India g_asutkar@yahoo.com Abstract— The paper presents a Field Programmable Gate Array based digital logic emulator capable of implementing Boolean functions which forms a platform for the design of higher combinational and sequential logic circuits. A Wireless Sensor Node has also been designed and implemented to exhibit the functionality of the node’s transmitter, receiver and main controller before the actual deployment. RTD Pt100 temperature sensor has been used along with ATmega8L as an input to the transmitter. The FPGA implementation of the system and the simulation results of all the modules have been presented in support of the work. Keywords— FPGA, WSN, FSM, CRC I. INTRODUCTION The emulation of designs plays a key role in reducing the hardware verification cycle. Emulation is a hybrid approach where the functions of a system can be duplicated which leads to the design analysis and rectifications in case of errors. Microcontroller based emulators ruled the markets earlier however, due to its incompatibility with the high speed peripherals they sooner got replaced by Field Programmable Gate Array (FPGA) based emulators. The system presented consists of a digital logic emulator block along with a Wireless Sensor Node which is the most significant component of a WSN network. The design of a digital logic emulator makes possible the implementation of logic functions. Besides digital logic, emulation of other complex systems such as a wireless sensor node that forms an integral part of Wireless Sensor Network (WSN) proves to be a great aid to find the design flaws and resolve them before the actual deployment of the node in remote inaccessible areas. II. Fig. 1.System Block Diagram Prior to the actual manufacturing process and deployment of the sensor nodes a simulation and validation phase is essential to remove the design flaws. A circuit can thus be designed and tested well in advance. The work presents the use of logic emulator as an encryption key generation tool for the transmitter. The input to the transmitter is the temperature sensed by Pt100 temperature sensor. This data is encrypted using the logic emulator for security purposes. Before the transmission of this data, the Cyclic Redundancy Check (CRC) block is used to generate the CRC checksum which is appended to the encrypted data and transmitted to the receiver. The transmitter begins the data transmission only after the reception of the beacon from the receiver. The transmission can be continued for fixed number of clock cycles or until an acknowledgment is received from the receiver. The Wireless Sensor Node has been modeled using Finite State Machine (FSM) as shown. Fig. 2.The state diagrams for the realization of (a) Transmitter consisting of Idle, Receive Beacon, Send Data and Receive Acknowledgement states, (b) Receiver consisting of Idle, Send Beacon, Receive Data, Send Acknowledgement and Device states and (c) Main Controller consisting of Idle, Gating Enable and Control Mode states. 978-1-4799-2827-9/13/$31.00 ©2013 IEEE