IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 4, Ver. I (Jul-Aug. 2014), PP 16-22 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org www.iosrjournals.org 16 | Page Domino Logic Topologies of OR Gate with Variable Threshold Voltage Keeper Vijay Singh Rathor 1 ,Saurabh Khandelwal 2 , Shyam Akashe 3 1Research Scholar ITM Universe, Gwalior, India 2,3Dept. of ECED ITM University, Gwalior India Abstract:In this paper, we tend to take four domino circuit topologies to boost the strength and lower the consumption of power. A high speed and noise immune domino logic circuit is given that uses the property of the footer semiconductor to raise the sensitivity of the dynamic node to noise and eventually in improved performance. Dynamic logic circuits are used for prime performance and high speed applications. We tend to analyze and compare completely different domino logic style topologies for lowering the sub-threshold outpouring current in standby mode NMOS block , increasing the speed and increasing the noise immunity. We tend to compare power, delay, and Power Delay Product (PDP) of various topologies. Simulation is finished employing a 45nm cadence tool for eight input OR circuit. Our projected circuits scale back power consumption by 100 percent to 35 the troubles, improvement of unity noise gain of 39% to 85% and have a higher figure of advantage as compared to conditional keeper domino. The simulation results unconcealed that prime Speed Conditional keeper Domino (CKD) circuit offers the most effective ends up in terms of reduction in delay and power consumption as compared to different circuits. Key words:CMOS, domino logic, keeper ratio, Standby power, Noise immunity, Lower power design. I. Introduction Domino logic is incredibly quick and needs less space as compared to static CMOS logic. It's utilized in a high performance essential system like microchip, multiplexor etc. because the technology is scaled down, over voltage is reduced. This reduces the ability consumption. The brink voltage is additionally scaled to take care of the desired performance. Low threshold voltage of the electronic transistor, increase the sub threshold AND circuit chemical compound outpouring current [1, 2]. However, low threshold voltage makes the domino circuit a lot of at risk of input noises. The most supply of noise signal in deep-submicron circuits are XT, outpouring current, charge sharing and provide noise. These noise signals scale back the lustiness of the domino circuit. High outpours current discharges the dynamic node and build the logic failure of the domino circuit. The keeper is sized weaker than the pull-down network, so as to permit quick analysis, whereas maintaining Associate in Nursing equal precharge-evaluation delay. The keeper quantitative relation K is outlined as K= µp  w L  keeper transistor µn  w L  evalution transistor (1) Where W and L denote the dimensions of an electronic transistor, µp and µn are the mobilities of hole and electron, severally. The dimensions of the pull down network is mounted and therefore the size of the keeper is variable. Increasing the worth of K improves the lustiness, however, has two negative effects on power consumption. Initial dynamic and output node capacitance will increase, that increase change power consumption. Second, it will increase the rivalry, current between the keeper and therefore the pull down network. That will increase the short power consumption. Up to a size of the keeper conjointly increase the delay of the domino circuit [3-7]. This technique isn't a reliable answer as a result of it will increase the speed and power consumption of the domino circuit. Associate in nursing different standard technique to boost circuit, lustiness are victimization high threshold voltage electronic transistor at the expense of speed [8-11]. Totally different techniques are planned within the literature to deal this issue. High speed domino logic and conditional keeper domino are the effective technique as compared to standard apodous domino logic circuit. During this paper, we tend to propose 3 lustiness footed domino logic circuits and one apodous domino logic circuit. These circuits use atiny, low voltage at the supply of the pull down network within the standby mode. The rest of the paper is organized as follows.