2490 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 57, NO. 5, OCTOBER 2010 A Low Noise Pixel Architecture for Scientific CMOS Monolithic Active Pixel Sensors Rebecca E. Coath, Jamie P. Crooks, Adam Godbeer, Matthew D. Wilson, Zhige Zhang, Marcel Stanitzki, Mike Tyndel, and Renato A. D. Turchetta, Member, IEEE Abstract—This paper presents the design and characterisation of FORTIS (4T Test Image Sensor), which is a low noise, CMOS monolithic active pixel sensor for scientific applications. The pixels present in FORTIS are based around the four transistor (4T) pixel architecture, which is already widely used in the commercial imaging community. The sensor design contains thirteen different variants of the 4T pixel architecture to investigate the effects of changing its core parameters. The variants include differences in the pixel pitch, the diode size, the in-pixel source follower, and the capacitance of the floating diffusion node (the input node of the in-pixel source follower). Processing variations have also been studied, which include varying the resistivity of the epitaxial layer and investigating the effects of a special deep p-well layer. By varying these parameters, the 4T pixel architecture can be opti- mised for scientific applications where detection of small amounts of charge is required. Index Terms—4T pixel, active pixel sensors, CMOS image sen- sors, high resistivity epitaxial layer, image sensors, low noise image sensor, pinned photodiode, radiation hardness, random telegraph signal noise. I. INTRODUCTION T HE scientific community often requires advanced image sensors, where the requirements can include high sensi- tivity, low noise, high charge collection efficiency and a tol- erance to radiation. CMOS Monolithic Active Pixel Sensors (MAPS) can achieve these requirements. Low noise and high sensitivity are of concern in applications where detection of small amounts of charge is required. One ex- ample of this is in high energy physics, where charge from min- imum ionising particles (MIPs) needs to be detected for deter- mining the rate and/or the position of the particles. If the noise level is too high, the MIP (typically a few hundred electrons) will go undetected. The sensitivity is related to the conversion gain of the pixel (the number of volts generated per electron), which if low, a MIP will not produce enough signal to be suc- cessfully read by the rest of the circuitry [1]. Charge collection efficiency should also be considered when determining whether a technology is suitable for the desired ap- plication. If complex in-pixel circuitry is required, then it is de- sirable to use both PMOS and NMOS transistors. However, due Manuscript received November 16, 2009; revised March 02, 2010; accepted May 13, 2010. Date of publication July 19, 2010; date of current version October 15, 2010. This work was supported by a grant from the Science Technology Facilities Council (STFC) U.K. The authors are with the Rutherford Appleton Laboratory, Science and Technology Facilities Council, Oxfordshire OX11 0QX, U.K. (e-mail: re- becca.coath@stfc.ac.uk). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNS.2010.2052469 Fig. 1. The FORTIS 1.0 sensor. to the fabrication of PMOS transistors inside n-wells, secondary charge collection areas form, reducing the amount of charge col- lected by the diode [2]. Charge collection efficiency is also degraded by crosstalk ef- fects. Charge generated far away from the diode will diffuse within the epitaxial layer and may not be collected by the pixel closest to where it was generated. This can lead to a reduced timing resolution and charge sharing across multiple pixels [3]. In the field of particle physics, this problem can disguise the actual location of where a MIP hit, as well as decreasing the charge available to be detected by the pixel which it actually hit, which if teamed with high noise, can leave the MIP undetected. In the colour imaging world, crosstalk between pixels can lead to blurring of colours, which requires often complex correction techniques to be incorporated off-chip [4]. We have been developing a novel process called INMAPS [5]. INMAPS is a 0.18 m CMOS Image Sensor process which addresses the issues of poor charge collection efficiency and crosstalk. We have also been investigating the four transistor (4T) pixel architecture for low noise and high conversion gain to give increased sensitivity to small amounts of charge. Both of these developments are demonstrated in FORTIS (4T Test Image Sensor). FORTIS is shown in Fig. 1, and explores several geometric variants of the 4T pixel under different processing conditions to optimise the architecture for low noise and high conversion gain. The pitch of the pixel was also investigated, as scientific applications generally require larger pixels to increase the total amount of charge collected at the cost of a reduced resolution. The contents of this paper are as follows. Section II will dis- cuss the technologies involved in the INMAPS process and the 4T pixel architecture. Section III will discuss the FORTIS sensor developed using these technologies, and Section IV will present 0018-9499/$26.00 © 2010 IEEE