International Journal of Advancements in Research & Technology, Volume 3, Issue 7, July-2014 142 ISSN 2278-7763 Copyright © 2014 SciResPub. IJOART Equal and Unequal Memory Partitioning and Task Scheduling for Multi-Processor System On Chip Jenitha A 1 Dr. Elumalai R 2 1. Associate Professor, Dept of ECE, EPCET, Bidrahalli, Virgonagar Post, Bangalore – 49. Karnataka. Email : 28jenitha@gmail.com, Phone : 9449680553 2. Professor and Head, Dept of IT , MSRIT, Mathekeri, MS Nagar , Bangalore. Karnataka. Email : elumalai.epcet@gmail.com Phone : 9448826813 Abstract: - The growing trend in embedded system is to deploy a Multiprocessor system on chip (MPSoC). MPSoC has heterogeneous processing elements, levels of memory hierarchy and input/output component which are linked together by an on chip interconnect structure. Such architectures provide the flexibility to meet the performance requirement of multimedia application while respecting constraint on memory, cost, size, time and power. The MPSoC is an attractive solution for increase in complexity and size of embedded applications. While embedded system becomes increasingly complex, the increase in memory access speed has failed to keep up with processor speed. This makes the memory access latency a major issue in scheduling the task of an embedded application on the processor and partitioning the memory among the processors are two critical issues in such systems. This paper presents an integrated approach to task scheduling and SRAM memory partitioning to reduce the execution time of embedded applications. Keyword:- MPSOC, Task scheduling, Memory partitioning, SRAM I. INTRODUCTION Due to clock and power constraints, architecture with multiple processor on a single chip have become attractive solution to achieve performance in both high end and low end computing Multiprocessor with large number of different processing cores are now common for variety of reasons, especially in embedded systems. MPSoC consist multiple heterogeneous processing element, memory hierarchy, input/output components which are linked together by an on chip interconnect structure. A critical component of a chip multiprocessor is its memory subsystem. This is because both power and performance behaviour of a chip multiprocessor is largely shaped by its on-chip memory. While it is possible to employ conventional memory designs such as pure private memory or pure shared memory, such designs are very general and rigid, and may not generate the best behaviour for a given embedded application. Execution time predictability is the critical issue for real time embedded applications; this means that data caches are not suitable and hard to model the exact behavior and to predict the execution time of tasks. Software controlled memories allow execution times to be predicted with accuracy. There is a large number of complex embedded applications consisting of multiple concurrent real Time tasks [1]. The problem of scheduling is weighted directed acyclic graph (DAG), also called a task graph or macro dataflow graph, to a set of homogenous processor to minimize the completion time. The tasks can be scheduled on different processors. To alleviate such problems, many modern MPSoC systems use IJOART