REVIEW PAPER International Journal of Recent Trends in Engineering, Vol 2, No. 8, November 2009 36 Design & Simulation Of High Gain Operational Amplifier For 12 Bit Pipelined Analog To Digital Converter Using Reduced Complexity Algorithm Neeru Agarwal 1 , S. C. Bose 2 1 Department of Electronics and Communication Engineering, Amity University, Noida, India 2 CEERI (CSIO) Pilani, Rajasthan, India Email: eng.neeru@gmail.com Abstract---This paper describes the design and analysis of High gain and widest bandwidth operational amplifier for Analog to Digital conversion application. Different Techniques are used to enhance the output characteristics performance. These amplifiers demonstrate the highest frequency and widest bandwidth of operation for amplifier using reduced complexity algorithm. This paper presents an improved circuit technique to improve the output performance. In this algorithm we are using merely a single operational amplifier for multiplication as well as amplification which enhance the power consumption and output characteristics without any degradation. Switched Capacitor Operational amplifier technique is used to reduce more power consumption. This Proposed work presents an improved architecture with reduced circuit components and complete circuit realization of its individual circuit blocks. This work is an effort to apply circuit techniques to implement a low cost, high-resolution A/D converter that can be easily integrated with a standard CMOS technology. This Proposed architecture is analyzed at 0.35μm technology using Mentor Graphics at 3.3V power supply. Advantages and disadvantages of the architecture are also discussed. Good agreement between measured and simulated results indicates the validity of our design methodology. Keyword-- power efficiency, residue voltage, operational amplifier, CMOS technology I.INTRODUCTION Technology scaling is the main thrust behind the advancement of CMOS technology. More and faster transistors are crammed onto integrated circuits with each new technology generation. The increased number of transistors and the enhanced clock frequency lead to a significant increase in the power consumption with each new technology generation [2]. As ADCs are typically power optimized for only a single operating speed, a power scaleable ADC affords minimal power consumption over a broad range of operating speeds in a single circuit [4]. In this paper, we describe the analysis and design of High gain and widest bandwidth operational amplifier. In addition, a power-scaleable ADC is of great utility in reducing design efforts as a single ADC can be targeted for a variety of applications each with vastly different performance requirements with respect to power and speed. Here we use the high gain and widest bandwidth amplifier with improving simulation results that enhances the performance of the proposed architecture. An effective method is the operational amplifier sharing technique which enhances the output performance. The amplifier sharing between two successive pipelined stages, not only can halve the power consumed by the amplifiers, the die area can be also smaller. Section II describes the proposed architecture and details the CMOS implementation of its building blocks. Experimental results are presented in Section III, and Section IV concludes this paper. II Operational amplifier using reduced Power Consumption with Power-On/Off An advantage of this operational amplifier which rapidly and completely powers on and off is that it can be speedily powered on only when needed, and powered off when not required. The sample-and-hold circuits of this work only have need of the opamp during the hold state, hence, to further decrease power, the op amps are powered off during the sampling phase of sample and hold. To measure the amount of power reduction afforded by powering off the opamps in the sampling phase, in the ADC mode the op amps can be programmed to be powered on or off through the sampling phase[4]. As high-speed ADCs normally do not completely power off the opamps in the sampling phase, by determining ADC power with the op amps always on and always off in the sampling phase, respectively, the power savings afforded can be calculated. © 2009 ACADEMY PUBLISHER