SYNTHESIS OF LOG-DOMAIN FILTER WITH WELL-DEFINED OPERATING POINT Zhan Xu and Ezz I. El-Masry Dept. of Electrical & Computer Engineering, Dalhousie University, P. O. Box 1000, Halifax, NS, Canada, B3J 2X4 Email: ezz.el-masry@dal.ca ABSTRACT A new systematic approach for the design of n-th order log-domain filters is presented. By eliminating the bias uncertainty, proper working condition is guaranteed for log-domain CMOS realization. This approach is based on the inverse-follow-the-leader-feedback (IFLF) topology and DC negative feedbacks are introduced to define the bias condition. To illustrate the proposed approach, a fourth order low-pass filer is designed and simulated in HSPICE. 1. INTRODUCTION In recent years, low-voltage integrated circuits have received a lot of attentions with the scaling down of CMOS technology. With the benefit of large dynamic range, circuits working below the threshold voltage attract more attentions. The first log-domain circuit is introduced by Frey [1], which is current-mode circuit technique using instantaneous companding principle [2]. In log-domain circuits, the current is compressed logarithmically when transformed into voltage and is expanded exponentially when converted back to current. Hence the voltage swings are dramatically reduced making them almost independent of supply voltage therefore well-suited for low-voltage applications. CMOS log-domain filers are usually designed by converting a conventional bipolar junction transistor- based log-domain filter circuit to its weak-inversion CMOS equivalent. Those circuits usually self-biased to an unintended operating point because of the positive feed- back loops used in the log-domain circuits [3]. Unlike bipolar transistor, the CMOS transistor follows the logarithmical law only in weak-inversion region. Hence, this self-bias behavior could render the circuits useless in CMOS. The purpose of this paper is to present a new approach for the synthesis of n-th order log-domain filters with well- defined operating point. The basic log-domain building blocks are first presented and the operation point uncertainty is explored. A general synthesis method is proposed based on IFLF topology. The load effect is also analyzed and compensation formula is provided for the design. At last, a fourth order low-pass filter is design and simulated in HSPICE. Fig. 1 General log-domain structure 2. LOGDOMAIN BASICS 2.1. A general log-domain structure with log-in and log-out circuit CMOS log-domain approach is one of the methods that utilize nonlinear circuit to realize linear system. It utilizes the exponential relationship between the drain current and gate-source voltage of MOS transistor in the weak inversion region. The current flowing in the transistor and the voltage across the gate-source is subject to the following relations: ds s 0 I I exp(Vgs / U ) and gs 0 ds s V U ln(I /I ) where, 0 T U nV and s D0 I W/L I General log-domain structure is shown in Fig.1. The current signal is first logarithmically compressed by the log-in circuit and after processing the resulting signal is expand exponentially by the log-out circuit. 2.2. Log-domain integrators and summer To realize the nonlinear log-processing, inverting and non-inverting integrators shown in Fig.2 and Fig.3; respectively, are essential. For the non-inverting integrator, the current flowing into the capacitor is given by: ' 0 0 0 0 C(dV / dt) I exp[(Vin ' V ')/U ] (1) Multiplying both sides of equation (1) by 0 0 0 Is / U exp(V / U ) yields 0 m dV C g Vin dt (2)