ASIC Design of Reversible Multiplier Circuit Hatkar A. P., Hatkar A. A. E&TC Engineering Department Sir Visvesvaraya Institute of Technology Nasik, India arvind_hatkar@yahoo.com Narkhede N. P. Electronics Engineering Department Shri Ramdeobaba College of Engineering & Management Nagpur, India narkheden@rknec.edu Abstract—Reversible logic is very much in demand for the future computing technologies as they are known to produce low power dissipation having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Adders and multipliers are fundamental building blocks in many computational units. In this paper we have presented and implemented reversible Wallace signed multiplier circuit in ASIC through modified Baugh-Wooley approach using standard reversible logic gates/cells, based on complementary pass- transistor logic and have been validated with simulations, a layout vs. schematic check, and a design rule check. It is proved that the proposed multiplier is better and optimized, compared to its existing counterparts with respect to the number of gates, constant inputs, garbage outputs, hardware complexity, and number of transistors required. It has also been shown in Cadence’s tools that the reversible multiplier outperform the irreversible multiplier in terms of power dissipation. Keywords: - Reversible logic, Low Power CMOS, Wallace signed multiplier, Baugh-Wooley approach, standard reversible logic cells. 1. INTRODUCTION Power dissipation and therewith heat generation is a serious problem for today’s computer chips. The 30-year-long trend in microelectronics has been to increase both speed and density by scaling of device components. During this trend higher level of integration and new fabrication processes reduced the heat generation in the last decade. A more fundamental reason for power dissipation arises from the observations made by Landauer already in 1961 [1]. Landauer proved that using conventional logic, gate operations always lead to energy dissipation regardless of the underlying technology. More precisely, exactly kTln2 Joule of energy is dissipated for each “lost” bit of information during an irreversible operation. This phenomenon can be attributed to the fact that erasing a bit amounts to ignoring its present contents, which may in fact be unknown and resetting it to some standardized state (usually 0). This means that the system moves from a random state to an ordered state thus bringing down the entropy of the system. But according to second law of thermodynamics entropy of a system cannot decrease and hence heat is dissipated into the surrounding environment [2]. In contrast, Bennett [3] showed that energy dissipation can be reduced or even eliminated if computation becomes information-lossless. This does not hold for irreversible (conventional) circuits. But, reversible circuits, i.e. circuits where all operations are performed in an invertible manner, satisfy this criterion. Moreover, as also shown by Bennett, zero power dissipation on circuits will only be possible if the respective computation is made reversible. As a consequence, Landauer [1] (and later Bennett [3], Fredkin [4], Toffoli [5]) suggested the use of reversible circuits. These circuits have an equal number of input and output signals, whereby each input assignment maps to a unique output assignment. Since reversible circuits are by definition information-lossless, power dissipation resulting from Landauer’s principle, as described above, can be decreased or even eliminated. In the computational units, multiplication is one of the useful operations. Therefore, developing a signed multiplier circuit is necessary. In this paper, we have proposed Wallace reversible signed multiplier circuit by Toffoli gate (TG) [5], Peres gate (PG) [6], and Haghparast-Navi gate (HNG) [7, 8]. We implemented basic standard reversible cells in Cadence tool and used them in the design of Wallace reversible signed multiplier. The paper is organized as follows. Section 2 presents an overview of reversible logic and multiplier circuits. In Section 3 we introduced design of reversible and irreversible Wallace sign multiplier circuit. Section 4 described the CMOS implementation of reversible and irreversible circuits. Furthermore, we have analyzed and evaluated the proposed reversible signed multiplier circuit in Section 5, Section 6 suggest some future extensions and Section 7 concludes the paper. 2. BASIC CONCEPTS A. Reversible logic Quantum gates which are represented by unitary matrices have potentials to implement reversible logic circuits. Each Quantum gate represents a valid Quantum operation, which must be unitary and hence must be reversible. That is Quantum gates are reversible, unlike many classical logic gates. Reversible logic gate/circuit can be defined as follows: Definition 1: For an n input, m output logic gate, if there is a one-to-one correspondence between its inputs and outputs, and then this logic gate is reversible. Definition 2: A gate is reversible if and only if the (Boolean) function is bijective i.e. a gate is reversible if it maps each input vector into a unique output vector and vice versa. 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies 978-1-4799-2102-7/14 $31.00 © 2014 IEEE DOI 10.1109/ICESC.2014.16 47