1242 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 20, NO. 8, AUGUST 2002 Performances of the Data Vortex Switch Architecture Under Nonuniform and Bursty Traffic Qimin Yang, Member, IEEE, and Keren Bergman, Member, IEEE Abstract—The Data Vortex switch architecture has been proposed as a scalable low-latency interconnection fabric for optical packet switches. This self-routed hierarchical architecture employs synchronous timing and distributed traffic-control signaling to eliminate optical buffering and to reduce the required routing logic, greatly facilitating a photonic implementation. In previous work, we have shown the efficient scalability of the architecture under uniform and random traffic conditions while maintaining high throughput and low-latency performance. This paper reports on the performance of the Data Vortex architecture under nonuniform and bursty traffic conditions. The results show that the switch architecture performs well under modest nonuniform traffic, but an excessive degree of nonuniformity will severely limit the scalability. As long as a modest degree of asymmetry between the number of input and output ports is provided, the Data Vortex switch is shown to handle very bursty traffic with little performance degradation. Index Terms—Bursty traffic, Data Vortex switch architecture, photonic packet switch, switching fabric, uniform traffic. I. INTRODUCTION T RANSMISSION of data in optical fibers has enabled the delivery of enormous bandwidth in today’s communica- tion networks, especially with new technology developments in dense wavelength division multiplexing (DWDM) and Raman fiber amplifiers [1]–[4]. The challenges in optical networking have recently migrated from transmitting high-capacity optical signals over long distances to effectively switching and man- aging that data [5]. These functions, currently performed in the electronic domain, have built an emerging large bottleneck to the scalability and growth of optical networks. Photonic or optical switches present an attractive solution to the electronic bottleneck with promises of transparency, high capacity, and little electromagnetic interference (EMI). However, to deliver the necessary system performances, most existing switching architectures require intense processing and buffering, which can be realized easily in the electronic domain, but is still considerably challenging within the optical domain [6], [7]. Therefore, new switch architectures must be developed to accommodate the optical or photonic implementation, where the advantages of the optics such as bandwidth and transparency can be fully exploited while the disadvantages of the optics can be avoided. Manuscript received May 31, 2001; revised March 29, 2002. This work was supported by the Defense Advanced Research Projects Agency and by the National Security Agency through an agreement with NASA under Contract 960199 and by the National Science Foundation under Contract ECS98-00401. The authors are with the Lightwave Technology Laboratory, Department of Electrical Engineering, Columbia University, New York, NY 10027 USA (e-mail: qimin_yang@hmc.edu). Digital Object Identifier 10.1109/JLT.2002.800330 In [8], a multiple-level minimum-logic architecture, the Data Vortex, was proposed for large-scale low-latency packet- switching fabric. This novel architecture employs synchronous timing and distributed traffic-control signaling to avoid packet contention; therefore, the system achieves great simplicity, scal- ability, and high throughput. The hierarchical routing topology is carefully designed at each level so that packet deflection probability and deflection-induced latency are both minimized. The hierarchical routing procedure also facilitates the use of a wavelength-header-encoding technique to further simplify the routing function and the switching latency. Using DWDM within the data payloads further enhances high data throughput. In previous work, we have investigated the basic routing functionality, control signaling mechanism, and wavelength routing technique within an experimental test bed [9], [10]. In addition, our simulation results have shown that the Data Vortex packet switch achieves high scalability, low latency, and narrow latency distribution under uniform and random traffic conditions [11]. However, in practice, packet-switching systems are generally subject to nonuniformly distributed and/or bursty traffic. These factors may contribute additional congestion or deflections within the architecture; therefore, they may affect the switching latency performance and the throughput performance of the system. In this paper, we report on the robustness of the Data Vortex switch performances under these nonideal factors. The rest of the paper is organized as follows. In Section II, an overview of the Data Vortex architecture is described. In Section III, we characterize the system performances in terms of successful injection probability, mean latency, and latency distribution. The performance results under different cases of nonuniform traffic and bursty traffic will be discussed and com- pared. Finally, we present our conclusions in Section IV. II. ARCHITECTURE OVERVIEW The Data Vortex switching topology can be arranged as a collection of richly connected routing nodes on multiple fiber cylinders, as seen in Fig. 1. The switch fabric size is character- ized by two parameters and , representing the number of nodes along the angle and height dimensions, respectively. is typically set to be a small odd number ( 10), and is indepen- dent of the choice of . The available number of input/output (I/O) ports is given by . The number of cylinder levels scales as . In Fig. 1, a switch fabric of is shown with a top view of the routing tours and a side view of the interconnection patterns at each of the cylinders. Each cross point shown is a routing node, which can be labeled uniquely by the coordinates , where , , and . 0733-8724/02$17.00 © 2002 IEEE