International Journal of Scientific & Engineering Research, Volume 5, Issue 8,August-2014 957 ISSN 2229-5518 IJSER © 2014 http://www.ijser.org subthreshold SRAM bit cell topologies for ultra low power applications Mahipal Dargupally, T. Vasudeva Reddy Padmasri Dr. B.V Raju Institute of Technology,Dept. of ECE,(CVD),Narsapur,Medak(Dt),India Abstract— Ultra Low Power is one of the major concern in VLSI Industry recent years. One of the technique which used to improve the concept is Sub- threshold Logic Design. A Number of researchers considering this technique for developing ultra low power applications. The proposed paper is using Sub-threshold logic design for memory devices such as SRAM and observed the power consumption, leakage power and delay for different SRAM Bit Cells like 6T,8T,9T and 10T. It's used High Vth NMOS for reducing the power consumption and leakage power[1]. The comparative result between different SRAM Bit cells showing the percentage of reduction of power consumption and leakage power is improved in 8T SRAM and delay in 9T SRAM than that of 6T SRAM. the different technology libraries like 90nm, 45nm have been used for these SRAM bit cells design and analysis. CADENCE VIRTUOSO schematic editor is used for circuit design and analysis. Index Terms— Low Leakage, Low Power, SRAM, Sub-Threshold, Weak inversion. ——————————  —————————— 1 INTRODUCTION HE Digital sub-threshold circuit design has become a very promising method for ultra-low power applications. Cir- cuits operating in the sub-threshold region utilize a sup- ply voltage (VDD) that is close to or even less than the thresh- old voltages (Vth) of the transistors. This low VDD operation results in ultra low-power dissipation. The circuit operating from strong inversion, moderate inversion regions to weak inversion region can be known as sub-threshold operating region[2]. SRAMs comprise a significant percentage of the total area and total power for many digital chips. SRAM leakage can dominate total chip leakage. Lowering VDD for SRAM saves leakage power and access energy[3]. 6T-SRAM read and writes operations depend on static noise margin (SNM). Write operation is successful if bitcell becomes monostable and SNM value is negative. Read operation can be done if WL is ‘1’ & BL precharged to ‘1’. Sub-threshold SRAM provides an advantage in min- imizing total memory energy consumption and providing compatibility with minimum-energy sub-threshold logic. 2 BASIC SRAM BIT CELL DESIGN Fig.1 shows the standard 6T SRAM bitcell. it consist of two cross coupled inverters made up of M1,M3,M4,M6 and access transistors M2,M5[3]. the WORDLINE(WL) is connected to the gate terminal of an access transistors and BITLINE(BL) is connected to the drain terminal. WL is used to select the cell for accessing the transistor for operating the bit cell and BLs are used to perform the read and write operation.The written data is stored at the node 'Q' and its complement at the node 'QB'[3]. A. Write Mode The proper write operation can be done successfully by consideration of Aspect ratio(W/L) of nMOS and pMOS. in Fig1 :standard SRAM6T Bitcell operation sizing of transistors in SRAM bit cell nMOS should win the ratio fight with pMOS. if we want to write data'1' making the WL=1 and one of the bitline keeping High i.e BL=1 and BLB=0 then the value is been written as '1' at nodeQ and its comple- ment at nodeQB. B. Read Mode the read operation can be done by precharging the Bitlines i.e BL=BLB=1 and now making the WL=1. then one of the Bitline is making low value. the read value can be ob- served by using Sense Amplifier. 3 SUBTHRESHOLD SRAM BITCELL DESIGN This paper explores the design of SRAM cell with alternative Bitcells like 6T,8T,9T and 10T. the design of bitcells are used High Vth nMOS transistors for reducing the Leakage Pow- er[1]. the ratio's of nMOS and pMOS are maintained with de- sign considerations. the Drive transistors(M1,M4) should be stronger than that of Access transistors(M2,M5) to minimize the disturbance in the READ MODE. and in the WRITE MODE Access transistors should be strong than Load transis- tors(M3,M6) for successful write operation. T IJSER