An Analog Neural Network Processor and its Application to High-speed Character Recognition Bernhard E. Boser, Eduard Sackinger, Jane Bromley, Yann LeCun, Richard E. Howard, and Lawrence D. Jackel AT&T Bell Laboratories Crawford Corner Road, Holmdel, NJ 07733 Abstract-A high-speed programmable neural network chip and its appli- cation to character recognition are described. A network with over 130,000 connections has been implemented on a single chip and operates at a rate of over 1000 classifications per second. The chip performs up to 2000 multiplica- tions and additions simultaneously. Its datapath is suitable particularly for the convolutional architectures that are typical in pattern classification networks, but can also be configured for fully connected or feedback topologies. Com- putations are performed with 6Bits accuracy for the weights and 3Bits for the states. The chip uses analog processing internally for higher density and reduced power dissipation, but all input/output is digital to simplify system integration. Introduction Learning from example and the ability to generalize are two features that make neural networks attractive for pattern recognition applications. However, the computational re- quirements, data rates, and size of neural network classifiers severely limit the throughput that can be obtained with networks implemented on serial general purpose computers. Better performance is achieved with special purpose VLSI processors that employ parallel processing to increase the processing rate. Speed and data rates are not the only challenges faced by specialized hardware designs for neural networks. Because of the rapid progress of neural network algorithms, processors must be flexible enough to accommodate a wide variety of neural network topologies. Moreover, the size of neural networks is increasing steadily. Networks with several ten or hundred thousand connections are typical for high-accuracy pattern classifiers [l, 21, and this number is expected to grow further. To be economical, such networks must be implemented on a small number of chips. Moreover, the high-performance parallel- computing unit must be matched with an equally powerful interface to avoid bottlenecks. In this paper, the architecture and implementation of a special purpose neural network chip that addresses these issues are described. The circuit uses analog processing internally to exploit the low resolution requirements typical of neural network, but employs an all digital external interface to simplify system integration. The practicality of the design is illustrated with results from an implementation of a neural network for handwritten optical digit recognition with over 130,000 connections. The entire network fits on a single chip and is evaluated at a rate in excess of 1000 characters per second. 0-7803-0164-1/s1/00~-0415$01.0001991 IEEE 1-4 15