1 Variable Threshold MOS Inverter Realization Through Dynamic Threshold MOS Inverter K. Ragini, 1 Dr. M. Satyam, 2 and Dr. B.C. Jinaga, 3 1 G. Narayanamma Institute of Technology & Science, Department of Electronics and Communication Engineering, Hyderabad, India 2 International Institute of Information Technology, Hyderabad, India 3 School of Information Technology, Jawaharlal Nehru Technology University, Hyderabad, India 1 E-mail address :ragini_kanchimi@yahoo.co.in 2 E-mail address: Satyam@iiit.ac.in 3 E-mail address:jinagabc@gmail.com Abstract It is known that Dynamic threshold MOS (DTMOS) operation near sub-threshold region results in better current drive, with marginal increase in power dissipation compared to CMOS circuits, operated at lower voltages. This paper proposes a modified DTMOS approach, called Variable threshold MOS (VTMOS) Inverter. The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Detailed results on VTMOS Inverter have been presented. The performance characteristics of VTMOS inverter - The Power dissipation, Propagation delay ,Rise and Fall time delay, Power delay product and Noise margin with the substrate bias have been evaluated through simulation using H spice. The dependency of these parameters on frequency of operation has also been investigated. 1.0 Introduction Sub-threshold voltage operation of CMOS circuits is a common practice for lowering the power dissipation. This, invariably, results in increase in propagation delay and less output drive [1][2][3]. To combat this problem, circuits have been built by varying the substrate voltage along the gate voltage (DTMOS substrate is connected to gate)[4].This in turn has resulted in some increase in the power dissipation, compared to CMOS[5].In view of this, it is thought that operating the DTMOS architecture with a proper bias voltage applied between gate and substrate (VTMOS), might result in lowering of operating currents and power dissipation .With a view to examine this conjuncture, circuits based on VTMOS have been conceived and their performance has been analyzed. The aim of this paper is to communicate the results obtained through the simulations on VTMOS Inverter circuits .In the first instance dc transfer characteristics of the MOS devices under VTMOS operation have been estimated theoretically and also through simulations .These characteristics enable the prediction of performance characteristics of the VTMOS based circuits .The actual performance has been obtained through simulations .It has been found that VTMOS circuits do result in lower power dissipation compared to CMOS and DTMOS circuits while other performance characteristics remain almost the same. In the first instance the transfer characteristics of the MOS devices in the