A CMOS CURRENT-MIRROR AMPLIFIER WITH COMPACT SLEW RATE ENHANCEMENT CIRCUIT FOR LARGE CAPACITIVE 'LOAD APPLICATIONS Hoi LEE and Philip K. T. MOK Integrated Power Electronics Laboratory Department of Electrical and Electronic Engineering The Hong Kong University of Science and Technology Clear Water Bay, Hong Kong, China Tel.: (852)2358-85 17, Fax: (852)2358-1485, Email: leehoi@ee.ust.hk, eemok@ee.ust.hk ABSTRACT A new slew rate enhancement (SE) circuit incorporated into a current-nlirror amplifier. which does not affect the small-signal ffequency response of the core amplifier. is presented. With the proposed enhancenient circuit. simulation results show that more than 38 times iniprovenients in both tlie slew rate and the settling time are achieved. Experimental results show that with 28OpW power consumption. 1.7V/ps slew rate and 61011s settling time at 470pF loading capacitor. were obtained. 1. INTRODUCTION The settling behavior of an operational amplifier is very critical as it directly affects the perforniance of the circuits using the amplifier. The settling time can be divided into tlie slewing period and the quasi-linear period [l. 21. In particular. tlie quasi-linear period depends on the small-signal behavior of the amplifier while the slewing period depends on the large-signal behavior. For the large capacitive applications (the loading capacitor CL 2 1 OOpF). the settling time of single-stage amplifiers is restricted by its slewing period as tlie niaxiiiiuiii available current I , to charge up the loading capacitor is linlited for a given power consumption. hi fact. the slew rate SR is given by In order to improve the slew rate. several methods have been proposed [3-71. In this paper. a current-nlirror amplifier with a new slew rate enhancement (SRE) circuit is presented. The proposed SRE circuit differs from tlie previous works in three ways. hi order to avoid wasting power dissipation in the core amplifier during fast signal transient and placing constraints on the device size of tlie core amplifier. tlie slew enhancing current is applied directly to the output of the amplifier instead of the core amplifier. Also. tlie proposed SRE circuit is separated from the core amplifier in order to improve the design flexibility such that the minimum quiescent current and the small chip area are attained. Furthermore. in order to avoid increasing the noise and the input capacitance of the core amplifier that can degrade the PSRR of tlie amplifier. the fast signal transition is detected by tlie load devices instead of the input transistors of the core amplifier. The operation principle and the design considerations of the proposed SRE circuit are discussed and analyzed in Section 2 and Section 3. respectively. Simulation and nieasuremenl results of tlie current-iiirror amplifier with tlie proposed SRI5 circuit are included in Section 4 to justify the improvement in slew rate. Finally. tlie sunmiary is given ui Section 5. 2. OPERATION PRINCIPLE The current-mirror amplifier with the proposed SRE circuit is show in Figure 1. in which the small-signal behavior of the amplifier is detenilined by transistors Ml-Ml2 while the slewing' capability is provided by transistors Mdl-MdS. In the SRE circuit. Md3 and Mdl are used to detect tlie fast input step transition. Transistors Md5 and Md2 are current sources sourcing and suhg the dc currents to transistor Md6 and from trmsistor Mdl. respectively. hi this design. Md5 and Md2 are biased such that if they operate 111 saturation region. their drain currerits equal to I, and 1,. respectively. At the same time. Md3 and M:dl are biased with the dc currents 1 : and 13. respectively. As the drains of Md5 and Md6 are tied. together. during the nomial operalion. Md5 and Md6 are in fact biased with tlie same dc current I?. mliich is much smaller than I,. As a result. Md5 is forced to operate in the triode region and the drain voltage of Md5 is pulled up to tlie positive supply voltage. Then Md7 is in the cut-off region. Sinlilarly. transistors Mdl and Md2 are biased with dc current 13, which is much smaller than I4 so that Md2 is forced to operate in the triode region and the drain voltage of MdZ is pulled down 1.0 the negative supply voltage. Then MdS is in the cut-off region. Therefore. the SRE circuit does not affect the perforniance of the core current- mirror amplifier under nomial operation. When the amplifier is connected in unity-gain feedback configuration and a positive step voltage is applied to tlie positive input of the amplifier. the increase in tlie drain current Im causes an fiicrease in gate-source voltage of Md3 and leads to an increase in I?. When I2 is larger than Il. the drain voltage of Md5 is decreased and causes Md7 to be heavily tumed on. As a result. a huge current is generated to charge up tlie loading capacitor at the output. Wien the output voltage reaches to the value close to tlie 0-7803-6685-9/01/$10.0002001 IEEE 1-220 Authorized licensed use limited to: Roger Colbeck. Downloaded on November 12, 2008 at 17:47 from IEEE Xplore. Restrictions apply.