International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169 Volume: 2 Issue: 6 1679 – 1682 _______________________________________________________________________________________________ 1679 IJRITCC | June 2014, Available @ http://www.ijritcc.org _______________________________________________________________________________________ Implementation of a 4-Bit Direct Charge Transfer Switched Capacitor DAC and DWA DEM technique Madhu Gudgunti Student, Dept. of E&TC Maharashtra Institute of Technology Pune, India gudguntimadhu@gmail.com Prof. Mrs. A.A. Askhedkar Assistant Professor, Dept. of E&TC Maharashtra Institute of Technology Pune, India askhedkaranuja@gmail.com Abstract— The direct charge transfer switched capacitor DAC is one of the type of delta-sigma DAC which reduce capacitor mismatch effect. The switched capacitor DAC mainly suffers from mismatch among capacitors. Mismatches among the capacitor in DAC cause the nonlinearity between output and input. It also reduces Signal to Noise Distortion Ratio (SNDR). Dynamic Element Matching (DEM) technique is used to match the capacitors. According to element selection logic there are many types. In this paper Data Weighted Averaging (DWA) technique is used for mismatch shaping. In this paper the 4 bit DCT-SC-DAC and DWA-DEM technique is implemented using WINSPICE simulation software. Index Terms—∑-Δ DAC, DCT-SC-DAC, mismatch shaping, DWA, DEM _______________________________________________*****_________________________________________________ I. INTRODUCTION The demand for high performance and linearity increases in audio digital to analog converter. The analog output is dependent on digital input and also analog reference voltage. Oversampling DACs use quantization-noise-shaping to increase signal to noise ratio (SNR). The ∆-∑ DAC is the one of the popular type of oversampling DAC. Noise shaping requires that the DAC be clocked at a frequency much higher than the signal bandwidth. Fig.1. Block diagram of Delta-sigma DAC The Fig.1 shows the block diagram of ∑-∆ DAC. In ∑-∆ DAC the difference between two signals is measured and used to get good conversion. The interpolation filter is used to increase the sampling ratio of the input data from the Nyquist rate f N to Rf N , where R is the oversampling ratio. Oversampling ratio is the ratio of the clock frequency to (twice) the signal bandwidth. The main function of noise- shaping loop (NL) is to reduce the word length of the signal from N 1 to a much lower value, often to 1. Mainly switched capacitor DAC is used in delta-sigma DAC as internal DAC. Low pass filter gives noise free analog output voltage [6]. II. A 4 BIT DCT-SC-DAC The 16 level DCT-SC DAC is implemented in this paper. While converting the digital input into analog it also decreases noise and enhances power efficiency. The circuit shown in Fig.2 is 4-bit DCT-SC DAC. As shown in figure operational amplifier is integral part of DCT- SC-DAC. There is very basic relationship between number of bits and levels (number of capacitors) given as a=2 b , where „a‟ is levels and „b‟ represents number of bits. The input word to the circuit is given by thermometer code as x 1 to x 16 . If input word is 5, x 1 to x 5 will be 1 and rest are 0. When ɸ 1 =1 (reset phase) all the input capacitors are charged to V ref and C f is discharged. When ɸ 2 =1 (conversion phase) all the input capacitors (i.e. C 1 to C m ) are discharged into C f , resulting in an output voltage V out = (mC/C f ) V ref (1) Where m is integer value of the input word, C is value of input capacitor, C f is feedback capacitor and V ref is reference voltage to circuit [1]. Fig.2. Circuit Diagram of 4-bit DCT-SC DAC