Tutorial 3 High Level Design Validation: Current Practices and Future Directions Indradeep Ghosh Fujitsu Laboratories of America, Inc. 1240 E Arques Ave. MS 345 Sunnyvale, CA 94085, USA Tel: +1-408-530-4559 Fax: +1-408-450-4558 Email: ighosh@fla.fujitsu.com Mukul Prasad Fujitsu Laboratories of America, Inc. 1240 E Arques Ave. MS 345 Sunnyvale, CA 94085, USA Tel: +1-408-530-4628 Fax: +1-408-450-4558 Email: mukul@fla.fujitsu.com Rajarshi Mukherjee Calypto Design Systems 2903 Bunker Hill Lane, Suite 208 Santa Clara, CA 95054, USA Tel: +1-408-850-2316 Fax: +1-408-850-2301 Email: rajarshim@yahoo.com Masahiro Fujita Department of Electronic Engineering University of Tokyo 7-3-1 Hongo, Bunkyo-ku Tokyo 113-8656, Japan Tel: +81-3-5841-6673 Fax: +81-3-5841-6724 Email: fujita@ee.t.u-tokyo.ac.jp Contact author: Indradeep Ghosh Abstract With the increasing complexity of VLSI design and time-to-market pressures, two major paradigms have emerged to address the difficulties currently being faced by the industry. They are: (1) the use of higher levels of design abstraction and (2) efficient and seamless design reuse. The design and modeling of a chip at higher levels of design abstraction brings with it additional burdens of validation, verification and testing at these levels. This tutorial will discuss current industrial practices and academic research in design verification and validation at these levels—specifically RTL, behavioral, specification and system level. High level modeling using languages like UML and Esterel will be presented and the associated verification challenges highlighted. Verification engines on higher order logic like theorem proving and decision procedures will be discussed. The tutorial will touch upon mapping, abstraction and refinement techniques used to make traditional formal verification techniques such as model checking applicable at the specification level, using languages like C, SystemC, SpecC and System Verilog. Several difficult problems of sequential circuit equivalence checking, timed vs untimed model equivalence checking, and concurrent vs sequential design Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE