International Journal of Advanced Research Trends in Engineering and Technology (IJARTET) Vol. 1, Issue 3, November 2014 All Rights Reserved © 2014 IJARTET 10 Certain Investigation on High Performance Low Complexity Fir Filter Architecture Used In Advanced Multipliers R.Chandru 1 , N.Deepak 2 Assistant Professor, Department Of Electronics and Communication Engineering Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India 1,2 Abstract: In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This project presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary- based common sub expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. I. INTRODUCTION With the increasing level of device integration and the growth in complexity of micro-electronic circuits, reduction of power efficiency has come to fore as a primary design goal while power efficiency has always been desirable in electronic circuits. The finite impulse response (FIR) digital filter is the fundamental element of digital signal processing (DSP) systems. The disadvantage of using digital FIR filters is that it involves lot of computations to process a signal. The implementation cost and power consumption are also high because of computational complexity. The complexity of the FIR filter is dictated by the complexity of the coefficient multipliers. The multipliers are the most expensive blocks in terms of area, delay, and power in a FIR filter structure. As shifts are less expensive in terms of hardware implementation, the design problem can be defined as the minimization of the number of addition/subtraction operations to implement the coefficient multiplications. The complexity of the multiplier block (MB) in a FIR filter is reduced, if implemented as shift-adders and sharing common sub- expressions. In order to reduce the complexity of the filter, the filter coefficients are encoded using the pseudo random floating point method; however it is limited to filter lengths less than 40. The methods are only suitable for fixed logic filters where the coefficients are fixed. Several reconfigurable FIR filters have been proposed by researchers and are discussed in detail [1–3, 9, 13, and 14]. These architectures are appropriate only for relatively lower-order filters and not suitable for channel filters in communication receivers. The idea is to pre- compute the values such as 0x, 1x, 2x, 3x, 4x, 5x, 6x and 7x, where x is the input signal and then reuse these pre- computations efficiently using multiplexers. The BCSE method proposed in [7] provides improved adder reductions leading to low complexity FIR filters. Re configurability of the FIR filters is not considered in [7] though. The concept of reconfigurable multiplier blocks (ReMB) is proposed in [3]. The ReMB generates all the coefficient products and a multiplexer selects the required ones depending on the input. The proposed reconfigurable FIR filter architecture, (processing element architecture), is shown in Fig. 1. The idea is to pre- compute the values such as 0x, 2x, 4x, 6x, 8x, 10x, 12x, 14x, where x is the input signal, then reuse these pre computations efficiently using multiplexers. This computation sharing multipliers (CSHM) can be used to realize efficient, low complexity FIR filter design.