CMOS CIRCUITS FOR THERMAL ASPERITY DETECTION AND RECOVERY IN DISK-DRIVE READ CHANNELS * Aaron Lee Paul Hurst Kiyoshi Fukahori Dept. of ECE Dept. of ECE TDK Semiconductor UC Davis UC Davis Mountain View, CA (now with AMD) ABSTRACT A thermal asperity detection and recovery scheme for a disk-drive read channel is presented. The circuit design and simulation results for two key blocks, the AC coupler and its tuning loop, in a 0.5μm CMOS process are described. 1. INTRODUCTION In a modern disk drive, the read head flies so close to the media surface that they occasionally come into contact with each other. When this happens, a large voltage is generated at the output of the read head preamp, and this is called a thermal asperity (TA) [1]. Modern read channels include a TA detection and recovery circuit as part of the front end [2], which is shown in Fig. 1. The read signal from the preamp, V in , which is a band- pass signal, is input to the AC coupler (ACC), which is a high-pass filter. Then the variable gain amplifier (VGA) amplifies the signal to give the output signal V out . This output signal is fed to the back end of the read channel to extract the data. Also, V out is fed into a 1-pole low-pass filter that has a low bandwidth and outputs the average value of V out , which is referred to as the baseline. The baseline is a constant (zero) under normal operation. However, when a TA occurs, the baseline experiences a large shift as shown in Fig. 2. A large baseline shift makes data detection difficult and can cause bit errors, as the large amplitude change typically causes clipping in the VGA. The amplitude of the baseline can be used to detect a TA event. If the amplitude of the baseline is larger than some threshold, the comparator output goes high in Fig. 1. Then a signal from the state machine reduces the AC coupler time constant which reduces the time required for the baseline to return to zero. When the baseline falls to within a threshold of zero, the time constant in the AC coupler is returned to its nominal value. Fig. 3 shows the schematic of the AC coupler. Each NMOS transistor is biased in the triode region with an on- resistance R f . Assuming an ideal opamp, the circuit has a zero at dc, a pole at -1/R f C f , and a high-frequency gain of -C in /C f . In normal operation, it should have a well controlled time constant so it passes the entire read signal. We chose R f C f = 32ns (-3dB frequency = 5MHz). A tuning circuit is used to set the on-resistance of the transistors by controlling V tune to set the time constant, as described in the next section. The AC coupler includes two additional transistors in parallel with each M1’ that are not shown in Fig. 3. These transistors are identical to M1’, and they are normally off with their gates tied low. If a TA is detected, the gates of these transistors are connected to V tune , reducing the time constant by a factor of three to more quickly return the baseline to zero. A folded-cascode opamp [3] is used in this AC coupler to achieve high gain, large bandwidth and large output swing. With C in =C f , the opamp must have a unity-gain bandwidth that is about equal to the data rate. Here, the target data rate was 800Mbps, so this opamp dissipates a significant amount of power. To save power, the tuning circuit does not use a replica(s) of the AC coupler. 2. TIME CONSTANT TUNING CIRCUIT A tuning circuit sets the on-resistance R f in the AC coupler so that R f C f is constant despite changes in C f due to process variations. For a NMOS device in the triode region with V DS << V GS - V t , the on-resistance R f is given by ( 29 1 1 , f m GS t R W g k V V L 2245 = ′ - (1) so the on-resistance can be varied by adjusting V GS . Eqn. (1) also shows the on-resistance R f is about equal to 1/g m of an identical, saturated transistor with the same gate and source voltages [3]. Therefore, if we can generate gate and source bias voltages in a reference circuit to give C f /g m = 32ns and apply them to M1’, then R f = 1/g m and R f C f = 32ns. The tuning scheme used here is based on this idea. The reference tuning loop uses a Gm cell in feedback as shown in simplified form in Fig. 4 [4]. A constant current I R is pushed into the Gm cell, producing a voltage V o1 = I R /g m . φ 1 and φ 2 are two non-overlapping clocks with frequency f clock . During φ 1 , the capacitor C 1 is charged to V o1 . During φ 2 , the charge on C 1 is transferred to capacitor C H . Also, a constant current NI R is drawn from C H . The average value of the opamp output, V f2 , is used to tune the _________________ * This research was funded by UC MICRO Grant 01-084, with support from Broadcom, Intel, Metalink, TDK Semiconductor and TI.