A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable 2D and 3D Microprocessors Fayez Mohamood Michael B. Healy Sung Kyu Lim Hsien-Hsin S. Lee School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332 {fayez, mbhealy, limsk, leehs}@ece.gatech.edu ABSTRACT Power delivery is a growing reliability concern in micropro- cessors as the industry moves toward feature-rich, power- hungrier designs. To battle the ever-aggravating power con- sumption, modern microprocessor designers or researchers propose and apply aggressive power-saving techniques in the form of clock-gating and/or power-gating in order to operate the processor within a given power envelope. However, these techniques often lead to high-frequency current variations, which can stress the power delivery system and jeopardize reliability due to inductive noise (L di dt ) in the power sup- ply network. In addition, with the advent of 3D stacked IC technology that facilitates the design of processors with much higher module density, the design of a low impedance power- delivery network can be a daunting challenge. To counteract these issues, modern microprocessors are designed to operate under the worst-case current assumption by deploying ade- quate decoupling capacitance. With the lowering of supply voltages and increased leakage power and current consump- tion, designing a processor for the worst case is becoming less appealing. In this paper, we propose a new dynamic inductive-noise controlling mechanism at the microarchitectural level that will limit the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the ac- cess patterns of microarchitectural modules, our mechanism can effectively limit simultaneous switching activity of close- by modules, thereby leveling voltage ringing at local power- pins. Compared to prior art, our di/dt controller is the first that takes the processor’s floorplan as well as its power-pin distribution into account to provide a finer-grained control with minimal performance degradation. Based on the evalu- ation results using 2D and 3D floorplans, we show that our techniques can significantly improve inductive noise induced by current demand variation and reduce the average current variability by up to 7 times with an average performance overhead of 4.0% (2D floorplan) and 3.8% (3D floorplan). 1. INTRODUCTION High-performance, power-conscious microprocessors exhibit varying current demands depending on the execution char- acteristics of a given program. For a high frequency micro- processor, any abrupt change in current demand (referred to as di/dt) will result in high-frequency inductive noise that leads to voltage ringing in the power-supply network, thereby posing a serious issue in circuit reliability. This is especially a concern in high-frequency processors where the supply-voltage needs to respond and stabilize to vary- ing current demands without violating stringent timing con- straints. In the worst case, overshoot or undershoot in the power supply network can adversely flip data values in the data path, resulting in incorrect computation. To address this reliability issue, processors are often over-designed, typ- ically with the use of an excessive amount of decoupling capacitors (decap) that can warrant reliable operations un- der the worst case current consumption scenario. However, for increasingly complex processors, inserting an overly ex- cessive amount of decaps enlarges the chip area and at the same time exacerbates the leakage power. Moreover, signifi- cant design effort and cost of worst-case design is inevitable for managing the infrequent cases where programs exhibit the maximum level of varying current demands during the course of execution. Traditional technology scaling for CMOS is one reason that causes a high variability in current flow within a pro- cessor. As the dimension of devices keeps shrinking, the supply voltage is reduced as well in order to meet the gate- oxide reliability requirement. This lowered supply voltage imposes a smaller absolute noise margin, exacerbating the inductive noise issue. On the other hand, the increasing number of available transistors on chip as well as the pursuit of ever-higher operating frequencies result in more power consumption. To mitigate power consumption and its ensu- ing thermal management problems, aggressive power-saving techniques such as clocking gating and/or power gating were widely studied and applied. Processors such as the Intel Pentium 4, Pentium M and IBM Power5 [14, 19, 3] use differ- ent levels of clock gating schemes to dynamically disable por- tions of the circuits that do not change states. At the mean- while, the industry has acknowledged the di/dt issue due to the extensive application of clock-gating and responded with architectural solutions. For instance, the L2 cache in the Power5 processor uses progressive clock-gating in different cache banks to mitigate the di/dt effect [14]. This is also one reason why ideal clock-gating, limiting power dissipation in active modules, is difficult to attain in practical designs. Conventionally, the worse-case current consumption can be profiled and gauged by exercising power virus programs [10]. These programs were written with a goal in mind — varying 1