Analytical Modeling of Ge and Si Double-Gate(DG) NFETs and the Effect of Process Induced Variations (PIV) on Device Performance Abhijit Pethe 1 , Tejas Krishnamohan 1 , Ken Uchida 1,2 , Krishna C. Saraswat 1 1 Department of Electrical Engineering, Stanford University, Stanford, CA 94305 2 Advanced LSI Technology Laboratory, Toshiba Corp., Japan pethe@stanford.edu, tejask@stanford.edu Abstract In this paper, we present a self-consistent, analytical model that includes carrier quantization; short channel effects (SCE) and calculates the ballistic currents in DGFETs. We use this new tool to compare the effect of SCE and process induced variations (PIV) on Silicon (Si) and Germanium (Ge) NMOS DGFETs. Our results show that in the case of DGFETs designed to meet the ITRS High Performance (HP) requirements, even with PIV, Ge performs better than Si. Whereas, due to its poorer SCE, in the case of DGFET designed to meet the ITRS Low Standby Power (LSTP) requirements, Ge performs worse than Si. 1 Introduction Due to its higher mobility and better transport properties, Ge seems to be an attractive candidate as a channel material in highly scaled MOSFETs [l]. However, its higher dielectric constant and lower band-gap make it very susceptible to Short Channel Effects (SCE) and Process Induced Variations (PIV). We present a methodology developed to compare scaled Si and Ge DGMOS devices. 2 Simulation Methodology The analytical simulation methodology that was used to model the DGFET is shown in Fig. 1. The effective masses that have been used in the calculations are as given in [2]. The carrier quantization effects based on advanced variational techniques [3] show excellent agreement, with those obtained by a numerical self-consistent 1-D Poisson-Schrödinger solver, over a wide range of substrate orientations and body thickness for both Si and Ge (Fig. 2). Analytical models are used to capture short channel effects [4,5]. Due to its higher dielectric constant , the short channel effects (DIBL and V T roll-off) in Ge are much worse than in Si (Fig. 3). The drive current for the device is calculated using a ballistic transport model [6,7]. The analytical simulator self-consistently solves for the ballistic currents, taking into account short- channel effects and carrier quantization. The appropriate gate work-function is used to meet the ITRS leakage current specification for a given node. Fig. 4 shows the I DS - V GS curves obtained by using this analytical simulator for different substrate orientations. Our results show that Ge<110> has the highest drive current. This is in