VDA-Place: Voltage-Drop-Aware Standard Cell Placement Antonios N. Dadaliaris†, George Dimitriou‡, Georgios I. Stamoulis‡ †Computer Science Department 2-4 Papasiopoulou St., Lamia 35100, Greece Electrical and Computer Engineering Department 37 Glavani St., Volos 38221, Greece ‡Electrical and Computer Engineering Department and Computer Science Department {dadaliaris, dimitriu, georges}@uth.gr ABSTRACT Voltage drop is becoming increasingly significant as integrated circuit (IC) fabrication processes move beyond 45nm, affecting both timing and reliability. We propose an IR-Drop based detailed standard cell placer that can achieve significant optimization of up to 6% for the timing of the critical path of a design. Our placer works incrementally to existing placers and is, thus, easier to integrate into existing industrial design flows. KEYWORDS Algorithms, physical design, placement, voltage drop, IR-drop. 1 INTRODUCTION As the fabrication processes of integrated circuits (IC) progress beyond 45nm, the voltage drop on the power supply network becomes a very important issue, affecting both the timing and the reliability of the IC. Several academic and industrial solutions have been proposed for accurately estimating the voltage drop and for optimally designing [1], [2], [3], [4], [5], [6], [7], [8], [9], [10] the power supply network of an IC. The target of all estimation approaches is to identify which areas of the design suffer from high voltage drop that adversely impacts the timing of the gates in that area, and, consequently, the performance of the entire circuit if the aforementioned gates happen to be on the critical path of the design. In the case where the voltage drop of the area encompassing part of the critical path of a design appears to be outside the required voltage drop limit the only course of action can be taken in present industrial design methodologies is to redesign the power grid and recalculate the voltage drop until it falls within the prescribed limits. However, this can happen late in the design cycle and induce a significant delay in the design cycle of the IC. Furthermore, even if the critical path is within the voltage drop bounds, negative slack can be present, which can be fixed either by upsizing the gates of the critical path or by restructuring the logic and the gates that implement it. Both of the above actions late in the design process may cause unnecessary perturbations and impede the convergence of the design. The approach presented in this paper is a first attempt at altering the prevalent design methodology by addressing the timing issues that arise when the critical path of a design is in a high voltage drop area either within or outside the prescribed limit. The main idea is to alter the placement of the critical path gates in such a way that they are moved to low voltage drop areas, and, therefore, suffer less performance reduction due to voltage drop. In the case where negative slack persists at the end of the design process, moving the critical path cells to a low voltage drop area is equivalent to speeding up the circuit under worst-case conditions, removing thus negative slack and providing another design knob that can be tweaked to optimize the design without the significant overhead that is introduced by extensive circuit or logic changes Proceedings of the International Conference on Computer Science, Computer Engineering, and Social Media, Thessaloniki, Greece, 2014 ISBN: 978-1-941968-04-8 ©2014 SDIWC 200