Electromigration: Estimation methodology for the sub-45nm era George Floros†, George Dimitriou‡, Georgios I. Stamoulis‡ †Computer Science Department ‡Electrical and Computer Engineering Department and Computer Science Department University of Thessaly {gefloros, dimitriu, georges}@uth.gr ABSTRACT Electromigration is starting to be one of the most significant problems considering reliability in integrated circuits design. The problem is induced by the large current density in circuit interconnections. Furthermore, the continuous reduction of the size of the integrated and the simultaneous increase of the currents flowing in semiconductors have introduced challenges in the design that increasingly are taking into consideration electromigration. The present work outlines the implementation of a tool that checks for violations in integrated circuits due to electromigration and calculates the mean time to failure based upon Black’s formula. Finally, the calculations take into account information like the self-healing effect and the mean current besides the maximum current, unlike most other academic and commercial tools. KEYWORDS Electromigration, reliability, CAD tools, VLSI, power grid, MTTF, interconnects. 1 INTRODUCTION Electromigration has been observed since more than a hundred years. Despite this, the most significant modeling of the phenomenon was produced empirically by Black [1] [2] in 1966: MTTF = AJ −2 expሺ   ሻ (1) where MTTF is mean time to failure, A is a constant depends on interconnect length and material, Ea is the activation energy (e.g., 0.6 eV for aluminum), k is the Boltzmann constant and, finally, T is the operating temperature. Besides the primary work that has been done by Black, recent studies have attempted to characterize in more detail the effects of electromigration but still Black’s equation is the most widely used. Electromigration can result in open circuits and shorts which cause the catastrophic failure of the circuit. However, electromigration, in modern sub-45nm in which process variability affects the shape and the electrical parameters of interconnects, can produce circuit failures due to higher voltage drop (i.e. higher than expected resistance values) long before the catastrophic open- or short-circuits impede correct operation of the IC. Models and tools have been developed to produce relatively accurate reliability assessments of interconnects in modern integrated circuits during the design and the layout process, in order to provide feedback for reliability issues before fabrication. From this point of view several tools like BERT (BErkeley Reliability Tool) [3], ITEM [4], ERNI (Electromigration Reliability of Networked Interconnects), and ERNI-3D [5] [6] have been proposed in the academia. BERT and ITEM compute reliability issues taking as an input a given layout while ERNI –ERNI-3D are based on a hierarchical methodology based on filtering of immortal interconnect trees. All the above tools are taking into account mainly the maximum dc current and self-healing effect in order to provide estimations. From our point of view, early planning reliability tools must be integrated in high level synthesis platforms in order to provide feedback, not only about electromigration but also for all Proceedings of the International Conference on Computer Science, Computer Engineering, and Social Media, Thessaloniki, Greece, 2014 ISBN: 978-1-941968-04-8 ©2014 SDIWC 173