Design and Implementation of Software-defined Radio (SDR) Based QPSK Modulator on FPGA Tarik Kazaz, Merima Kulin, Mesud Hadzialic Faculty of Electrical Engineering University of Sarajevo Sarajevo, Bosnia and Herzegovina { tarik.kazaz, mk15172, mhadzialic }@etf.unsa.ba Abstract—Software defined radio (SDR) technology enables implementation of wireless devices that support multiple air- interfaces and modulation formats, which is very important if consider proliferation of wireless standards. To enable such functionality SDR is using reconfigurable hardware platform such as Field Programmable Gate Array (FPGA). In this paper, we present design procedure and implementation result of SDR based QPSK modulator on Altera Cyclone IV FPGA. For design and implementation of QPSK modulator we used Altera DSP Builder Tool combined with Matlab/Simulink, Modelsim and Quartus II design tools. As reconfigurable hardware platform we used Altera DE2-115 development and education board with AD/DA daughter card. Software and Hardware-in-the-loop (HIL) simulation was conducted before hardware implementation and verification of designed system. This method of design makes implementation of SDR based modulators simpler ad faster. Index Terms—SDR, FPGA, QPSK, DSP Builder, NCO, RRC I. I NTRODUCTION The term software radio, which became later the term soft- ware defined radio, was first introduced by prof. Joseph Mitola [1], as an approach for implementing a re-programmable and re-configurable radio transceiver. Benefits and advantages of SDR transceiver systems became apparent after the develop- ment of a large number of standards for wireless commu- nication networks. The terminal equipment of operators was required to support specifications of more standards simulta- neously. This had required the need to implement a transceiver system that is able to support multiple encryption, modulation and signal processing techniques. Transceiver systems imple- mented in accordance with the concept of SDRs, represent a solution to these problems and challenges. There are also current studies relating to the implementation of intelligent Cognitive Radio systems, and the basis for this implementation is SDR. One possible approach for the realization of SDR transceiver systems is the use of FPGA hardware components. FPGA platform is attractive because of its good performance, low power consumption and configurability. Digital signal pro- cessing based on the use of FPGA chips has found application in many areas such as: Mobile Systems (3G and 4G), VoIP, multimedia, radar and satellite systems. On the other hand, PSK modulation is widely used in existing wireless technologies. Current and important appli- cations of QPSK modulation are in standards: LTE & LTE- ADVANCE, IEEE 802.11b-1999, IEEE 802.11g-2003 and IEEE 802.15.4. In QPSK, two successive bits in the data sequence are grouped together into a symbol. At the input, the QPSK modulator performs a serial to parallel conversion of the input bits, and then the conversion from unipolar to bipolar signal. After these operations, it is necessary to perform signal filtering to avoid signal distortion called intersymbol interference (ISI) [2]. After filtering, the modulating signal is ready to modulate the carrier. At the end the modulated signals, generated in two separate branches of the modulator (I and Q branch), are summarized and translated into an analog signal by a digital-to-analog converter. The signal at the output of QPSK modulator is mathematically represented as defined by the following equation [3]: s QPSK (t)= d I (t) cos (2πf 0 t) - d Q (t) sin (2πf 0 t) (1) Branches d I (t) and d Q (t) are defined as follows: d I (t)=  2E T cos  (2i - 1) π 4  (2) d Q (t)=  2E T sin  (2i - 1) π 4  (3) Where E is the energy per symbol, i =1, 2, 3, 4, 0≤t≤T . The differences between digital implementation of QPSK modulator on FPGA chip, and its conventional implementa- tion in analog electronics are significant. The conventional approach would require the decomposition of the presented system into subsystems, and the need for more hardware components. For example, the serial to parallel conversion of a series of input bits would require the use of a combination of D and T flip-flops [4]. Carrier generation would require the use of voltage controlled oscillator (VCO) and a phase shifter of 90 degrees. Multiplying the carrier and the modulating signal would require two mixers. In addition, for signal shaping it is necessary to use at least two filters. With the use of FPGA integrated circuits, the previously described QPSK modula- tor could be implemented almost entirely on a single chip along with an indispensable addition of an analog-to-digital converter. There is an obvious advantage and convenience of system implementation on FPGA chips. To realize the