2014 International Conference on Computer Communication and Informatics (ICCCI -2014), Jan. 03 – 05, 2014, Coimbatore, INDIA [978-1-4799-2352-6/14/$31.00 ©2014 IEEE] A Modified Novel Compressor based Urdhwa Tiryakbhyam Multiplier N.Rajasekhar M. Tech II year student Department of Electronics Engineering Pondicherry University Pondicherry, India rajpdtrkad.atr@gmail.com Dr.T.Shanmuganantham Asst. Professor Department of Electronics Engineering Pondicherry University Pondicherry, India shanmuga.dee@pondiuni.edu.in Abstract—With the advent of new technology in the domain of VLSI, communication and signal processing, there is an ever going demand for the high speed processing and low area design. In this paper, introduces modified compressor based multiplier architecture. This modified structure uses the 4:2 compressor and 7:2 compressor architectures. In addition to that it uses Vedic mathematics to get a high speed multiplication operation and low area design. The design and experiments carried were carried out on a Xilinx Spartan 3E series of FPGA and discussed about the results of area and speed. Keywords—High speed multiplier, 4:2 compressor, 7:2 compressor, modified architecture, vedic mathematics. I. INTRODUCTION The Processor speed greatly depends on its multiplier’s performance. This in turn raises the demand for multipliers high speed, at the same time maintaining low area and moderate power dissipation [1]. Over the past few decades, several new novel architectures are come for multipliers and have been designed and explored. Booth’s [2] and modified Booth’s algorithm based multipliers are quite popular in modern VLSI design but come along with their own set of disadvantages. In these multiplier algorithms, the multiplication process, involves several transitional operations before received at the finishing answer. The intermediate stages include several additions, subtractions and comparisons which reduce the speed exponentially with the total number of bits present in the multiplier and the multiplicand [6]. Since the speed is major concern, utilizing such type of architectures is not good approach since it involves several time consuming operations. In order to address the disadvantages of the above mentioned methods [7, 8] with respect to speed of opera ration, explored a new approach for multiplier design based on ancient vedic mathematics. Vedic mathematics is an Indian ancient and eminent approach which acts as a foundation to solve many mathematical challenges faced in the current day scenario. Vedic mathematics was existed in ancient India and re discovered by a popular great mathematician, Sri Bharati Krishna Tirthaji [9]. He divided the Vedic mathematics into 16 simple sutras (formulae). These Sutras deals with Arithmetic, Analytical, Algebra, Geometry, Trigonometry, etc. The simplicity in the Vedic mathematics sutras pays a way for its application in several prominent domains of engineering and technology like Signal Processing, Control Engineering and VLSI [10]. One of the highlights in Vedic mathematics approach is that the calculation of all partial products required for multiplication, are obtained well in development, much before that the actual operations of multiplication begin. These intermediate partial products are then added based on the Vedic mathematics algorithm to obtain the ending product. This in turn indications to a very high speed approach to achieve multiplication [11]. In this paper, explore a novel method to further enhance in speed of a Vedic multiplier by replacing the existing full adders and half adders of the Vedic mathematics based multipliers with compressors based adders. Compressors, in its several variants, are logic circuits which are skilled of adding more than 3 bits at a time as divergent to a full adder and capable of acting with a lesser gate count and higher speed in comparison with an equivalent full adder circuit [13]. II. VEDIC MATHEMATICS A. Urdhwa Tiryakbhyam Sutra Vedic mathematics is divided into 16 different sutras to perform to perform mathematical calculations. Among these sutras Urdhwa Tiryakbhyam is the most preferable and good enough algorithm to perform multiplication of integers as well as binary numbers. The term "Urdhwa Tiryakbhyam” originated from 2 Sanskrit words Urdhwa and Tiryakbhyam which means that “vertically” and “crosswise” respectively. Let us consider the two 8 bit numbers X7-X0and Y7- Y0, where 0 to 7 represent bits from the Least Significant Bit (LSB) to the Most Significant Bit (MSB). P0to P15represent each bit of the multiplied result [1]. It can be seen from