Institute of Electronics Engineers of the Philippines (IECEP) Journal Vol. 1, No. 1, pp. 19 – 26, July 2012. ISSN 2244 – 2146 (Print) Design and Implementation of Low Power Half Duplex Embedded Chip to Chip Communication via Microwire Bus Interface Angelo A. Beltran Jr. #*1 , Micaela Renee Bernardo #*2 # Department of Electronics Engineering, Technological Institute of the Philippines - Manila Arlegui St. Quiapo, Manila,Philippines 1 abeltranjr@gmail.com 2 michi_bernardo@yahoo.com * School of Graduate Studies Mapua Insti tute of Technology Muralla St. Intramuros, Manila, Philippines Abstract —Embedded systems rely on chip to chip communi- cations for exchange of data to be processed. Communication protocols between chips are complex and verification becomes consuming which leaves time and effort for the system designers. In addition, 32-bit microcontrollers and serial eeprom are gaining popularity as they are very suitable for high end processing and data storage. Furthermore, chip to chip communication has to be tailored and optimized to meet the demands of wide range applications. They pose significant challenges to the system designer. In this paper, we present a design methodology needed for chip to chip communication via microwire bus communication protocol interface that combines design and verification together to make it work and operate. A 32bit DSP-RISC based microcontroller and a serial eeprom chip is used to validate the microwire bus communication protocol scheme proposed in this paper. The modeling framework consists of hardware interfacing and software design steps formalized as finite state machines. Circuit design, software algorithm and different set of experimental test are presented in this work. The protocol is implemented and experiment shows data communication between chips without detectable error. The results are satisfactory for both hardware and software level hierarchy and proved the effectiveness of the proposed method. The benefits achieved from this development can be used to aid the system designer for generic chips used to implement the microwire bus communication protocol and verify their correctness. Keywords-chip communication, eeprom, finite state machine, microcontroller, microwire bus, protocol I. INTRODUCTION Chip to chip communication or multi chip packaging is of great importance in developing large scale digital systems [1]. Recent advances in very large scale integrated (VLSI) semiconductors have led to a family of advanced microcontrollers that can be of great benefit to designers of aerospace communication systems [2]. In a system, there are various types of memories like internal random access memory (RAM) at microcontroller, RAM at system on chip or external RAM, internal caches at microprocessor, read only memory (ROM), programmable read only memory (PROM) flash electrically erasable programmable read only memory (EEPROM), and memory addresses at the system ports. Submicrometre CMOS technology currently provides the possibility of integrating millions of transistors on a single chip [3]. The die pads which are always used in chip to chip communications limits the performance because they have parasitic capacitance therefore reducing the power consumed by chip to chip communication circuits is very important [3]. Processor speeds getting close to the gigahertz range, conventional buses are more and more becoming limiting factor for the performance of electronic computers [4]. There are several forms of chip to chip communication circuits that do not require the standard address bus and data bus wiring. Modern microprocessors try to reduce the effect of decreasing propagation delay and latency gap inside VLSI circuits by using larger on-chip caches and wider off-chip buses. Unfortunately, the resulting increase in pin count and board area makes the system goes up [5]. Microwire interface offers four signal lines and they have independent data-in (DI) and data-out (DO) lines as well as a chip select (CS) and a serial clock (SK). This serial memory allows us to store large amounts of information without giving up those general purpose input and output (I/O) lines. Compared to other non volatile memory solutions, serial EEPROM chips offer a lower pin count, smaller packages, lower voltages, as well as lower power consumption thus making it an excellent non volatile storage. The microwire reference comes from the fact that the two data lines data in and data out can be tied together plus a serial clock resulting in a device with three wires. A complete CMOS circuit system has to cope with high speed chip to chip communication [6]. This chips offer significant advantages over parallel devices in application where lower data transfer rates are acceptable. In addition to requiring less PCB space, serial devices allow microcontroller I/O pins to be conserved.