2014 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT) ISBN No. 978-1-4799-3914-5/14/$31.00 ©2014 IEEE 512 Performance Evaluation of MCML-Based XOR/XNOR Circuit at 16-nm Technology Node Amit Krishna Dwivedi 1 , Pragya Srivastava 2 , Farha Tarannum 3 , Smriti Suman 4 , Aminul Islam 5 1,2,3,4,5 Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra,Ranchi, Jharkhand, India 1 amit10011.13@bitmesra.ac.in, 2 pragya10008.12@bitmesra.ac.in, 3 fashu.farha@gmail.com, 4 smriti1214.11@bitmesra.ac.in Abstract—MOS current mode logic (MCML) is an emerging logic family which is gaining attention due to its high speed of operation, robust performance and presence of mere switching noise as compared to the CMOS logic family. In this paper we have explored various XOR circuits in terms of propagation delay (t p ), average power (PWR) and power delay product (PDP) at 16-nm Technology node. Variability analysis establishes High Speed 8T (HS-8T) XOR circuit as fastest and robust CMOS based XOR circuit among the other CMOS counterparts. Further, realization of XOR circuit is done using MCML topology. This paper also highlights various design issues in CMOS implementation and provides an analytical formulation of design using MCML to overcome different tradeoffs. MCML based XOR circuit proved to be even faster than High Speed 8T (HS-8T) XOR circuit. In particular, MCML based XOR circuit shows 107.384 × improvement in t p and 3.654 × improvement in PDP at nominal voltage of V DD = 0.7 V. Variability analysis establishes MCML based XOR circuit as the most resilient and immune to various electrical parameters. Keywords— average power (PWR); high speed; MOS current mode logic (MCML); XOR/XNOR circuit; power dealy product (PDP); propagation delay (t p ); variability; robust. I. INTRODUCTION The on-chip integration of various analog and digital circuits requires higher speed of operation with less power consumption. The conventional CMOS technology is not capable of providing an efficient solution to these requirements. The emerging class of MOS current mode logic (MCML) is proving to be a promising technology for the current trends of technology requirements due to its higher speed of operation. MOS implementation of current mode logic (CML) is preferred over bipolar CML because of scalability of its feature size and less power consumption with higher speed of operation [1] [2] [3]. XOR circuits are an elementary building block of various complex circuits. XOR circuit can be also used as a buffer or inverter by making one of its input low and one of its input high respectively. Many arithmetic logic circuits such as full adder, computational logic comparator, parity generator/checker for error detection circuits, and so on are designed using an exclusive-OR as their basic functional unit. Thus XOR circuits play a major role in determining the overall performance of these circuits. This paper investigates different types of XOR circuit in terms of different design metric such as propagation delay (t p ), power consumption and power dissipation. The optimal XOR circuit realized using CMOS logic is later compared with XOR circuit implemented using MOS current mode logic (MCML) topology. Although CMOS implementation possesses advantage in terms of static power dissipation but conventional CMOS cannot simultaneously satisfy requirements of both speed and power requirements for these circuits [4]. MCML provides high speed of operation with low supply noise generation and high noise immunity. These properties of MCML logic family help us to integrate analog and digital blocks on a single chip. The implementation using MCML logic family faces tough challenges due to its complex circuit design. These design issues are resolved to some extends by providing an efficient alternate design [4]. To verify the results, extensive simulations on HSPICE using 16-nm PTM (developed by the Nano scale Integration and Modeling (NIMO) Group at Arizona State University (ASU) [5] are carried out at nominal V DD of 0.7 V. The rest of the paper is organized as follows. Various XOR circuits are briefly examined in terms of different design metrics in the Section II. In Section III the XOR circuit is realized using MOS current mode logic (MCML) topology. Optimal circuit emerged from section II is compared with MCML based XOR. Finally the concluding remarks are given in Section IV. II. INVESTIGATION OF SIGNIFICANT XOR CIRCUITS The efficient design of XOR circuit is key requirement for many complex circuits as these circuits are developed using XOR circuit as their basic units. Different XOR circuits are thus analyzed thoroughly in this work. Fig. 1 shows the circuit diagram of 4T PTL based XOR circuit [6]. This circuit is devised using static CMOS inverter. The availability of the inverter gives signal level restoration and improves the driving capability of the circuit . However, output levels of this circuit are not appreciably matched. This is the demerit of this circuit. High Speed 8-transistor (HS-8T) XOR circuit shown in Fig. 2 [7] consists of transmission gates. The circuit delivers high speed of operation, but has comparatively high power