Characteristics of Si Integrated Antenna for Inter-Chip Wireless Interconnection A. B. M. Harun-ur RASHID  , Shinji WATANABE and Takamaro KIKKAWA Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima 739-8527, Japan (Received September 24, 2003; accepted November 28, 2003; published April 27, 2004) The characteristics of a small-size integrated dipole antenna on Si have been evaluated for use in inter-chip wireless interconnections and the measured characteristics are compared with the results obtained by 3D finite element simulation. The measured inter-chip transmission coefficients for a 0.02 mm 2 dipole antenna pair manually separated by 10.5 mm each other in the horizontal plane and in a omit plane where the receiver chip is 2.6 mm higher than the transmitter chip were 42.7 dB and 57.5 dB at 20 GHz when the antennas were fabricated on a high-resistivity Si substrate and on standard Si substrate, respectively. This shows the feasibility of using integrated dipole antennas for wireless clock distribution and data transmission in future 3D ICs or in stacked chip scale packaging. [DOI: 10.1143/JJAP.43.2283] KEYWORDS: wireless interconnects, integrated antennas, clock distribution, transmission gain, interference, ULSI 1. Introduction The fundamental limitations of conventional interconnect systems in reducing signal propagation delay has led to the proposal of intra-chip wireless interconnections using integrated antennas, 1–3) microstrip transmission lines 4–6) and optical networks. 7) Among these approaches, microwave clock distribution using integrated antennas can reduce the chip area used in interconnections while reducing the clock skew and dispersion thus enabling a high clock frequency. At the same time, the growing complexity in integrated circuit design such as the design of system on a chip (SoC) has increased the urgency for realizing 3D ICs and stacked chip scale packaging. Inter-chip wireless interconnections using integrated antennas are very promising for such systems with the potential of realizing very-high-frequency data and clock transmission while eliminating the need for complex wiring. However, studies on inter-chip wireless interconnects using integrated antennas have not yet been performed. In this paper, we report on the feasibility of inter-chip wireless interconnections using Si integrated antennas. The measured characteristics are compared with simulated results obtained by employing a 3D finite element method using the Ansoft HFSS program. The improvement of inter- chip signal transmission by the use of a high-resistivity Si substrate is also studied. 2. Antenna Test Structure Fabrication, Measurement and Simulation Figure 1 shows the conceptual diagram of the inter-chip clock and data transmission in stacked chip packaging using an integrated antenna. The transmitting antenna transmits clock and data to the receiver antenna within the chip or to another chip of the stacked package. Antenna test structures were fabricated on a 260-mm-thick Si wafer with a 0.5-mm- thick field oxide. A 1-mm-thick aluminum layer was sputtered on top of the oxide and patterned by electron beam lithography to form the antenna. The antenna length and width were fixed at 2 mm and 10 mm, respectively. Figure 2 shows various configurations used for the evalua- tion of inter-chip signal transmission. For reference pur- poses, intra-chip signal transmission, where the antenna distance is d 0 ¼ 3:0 mm, was evaluated first (Fig. 2(a)). This was followed by evaluation of inter-chip signal transmission with both chips placed on the same horizontal plane i.e. both chips at the same height (Fig. 2(b)). The gap between the two chips (d air ) was fixed at 0.5 mm so that the total horizontal antenna distance was d total ¼ 3:5 mm. Next, we evaluated inter-chip signal transmission with one chip 2.6 mm higher than the other and with a horizontal gap of 0.5 mm between the chips so that the total horizontal antenna distance was d total ¼ 3:5 mm (Fig. 2(c)) i.e. the two chips does not overlap each other. Finally we simulated inter-chip signal transmission with one chip 2.6 mm higher than the other and with both chips completely overlapping each other (Fig. 2(d)). We were not able to measure data for this configuration (Fig. 2(d)) because of the difficulties of placing the probe. Figure 3 shows the setup for the measurement of S-parameter. It consists of a HP8510C vector network analyzer, 6.0–26.5 GHz 180  hybrid coupler, signal-signal probes and a probe station. This setup converts the unbalanced signals from the network analyzer to balanced signals used to excite the dipole antenna. Semi-rigid cables were used to increase measurement reliability. Wafers were measured on a block of a thick (2.6 mm) low-k substrate placed on the metal chuck of the probe station. This was done to avoid the interference from the bottom metallic plate of the probe chuck and to eliminate the reactive near-field Fig. 1. Concept of inter-chip wireless signal transmission in stacked chip packaging. T x —transmitting antenna, R x —receiving antenna.  On leave from Bangladesh University of Engineering and Technology, Dhaka, Bangladesh. Japanese Journal of Applied Physics Vol. 43, No. 4B, 2004, pp. 2283–2287 #2004 The Japan Society of Applied Physics 2283