V.V. Das, J. Stephen, and Y. Chaba (Eds.): CNC 2011, CCIS 142, pp. 83–87, 2011. © Springer-Verlag Berlin Heidelberg 2011 Design of Efficient Reversible Parallel Binary Adder/Subtractor H.G. Rangaraju 1 , U. Venugopal 2 , K.N. Muralidhara 3 , and K.B. Raja 2 1 Department of Electronics and Communication Engineering, Government Engineering College, Chamarajanagar, Karnataka, India rang_raju@yahoo.com 2 Department of Electronics and Communication Engineering, University Visvesvaraya College of Engineering, Bangalore, Karnataka, India venu.ubaradka@gmail.com 3 Department of Electronics and Communication Engineering, P E S College of Engineering, Mandya, Karnataka, India Abstract. In recent years, Reversible Logic is becoming more and more promi- nent technology having its applications in Low Power CMOS, Quantum Computing etc. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible 8-bit Parallel Binary Ad- der/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number gates, Garbage inputs/outputs and Quantum Cost. It is observed that Reversible 8-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I and II. Index Terms: Reversible Logic, Garbage Input/output, Quantum Cost, Re- versible Parallel Binary Adder/Subtractor. 1 Introduction Energy loss is an important consideration in digital design. Higher level of integration and use of new fabrication processes have dramatically reduced the heat loss over the last decades. The power dissipation in a circuit can further be reduced by the use of reversible logic. Landauer’s [1] principle states that logic computations that are not reversible necessarily generate heat energy of KTln2 joules for every bit of informa- tion that is lost, where ‘K’ is Boltzmann’s constant and T the absolute temperature. Bennett [2] showed that zero energy dissipation is possible only if a computation is carried out in Reversible logic, as the amount of energy dissipated in a system is di- rectly related to the number of bits erased during computation. Contribution: In this paper, novel three design types viz., Design I, Design II and Design III Reversible 8-bit Parallel Binary Adder/Subtractor are proposed. The Re- versible gates such as Fredkin (F), Feynman (FG), Peres (PG) and TR are used. Or- ganization: The paper is organized into the following sections. The Background work