Lithography Simulation-Based Full-Chip Design Analyses Puneet Gupta a , Andrew B. Kahng a , Sam Nakagawa a , Saumil Shah b and Puneet Sharma c a Blaze DFM, Inc., Sunnyvale, CA; b University of Michigan, Ann Arbor, MI; c University of California San Diego, La Jolla, CA ABSTRACT Today’s design flows sign-off performance and power prior to application of resolution enhancement techniques (RETs). Together with process variations, RETs can lead to substantial difference between post-layout and on-silicon performance and power. Lithography simulation enables estimation of on-silicon feature sizes at different process conditions. However, current lithography simulation tools are completely shape-based and not connected to the design in any way. This prevents designers from estimating on-silicon performance and power and consequently most chips are designed for pessimistic worst-cases. In this paper we present a novel methodology that uses the result of lithography simulation for estimation of performance and power of a design using standard device- and chip-level analysis tools. The key challenge addressed by our methodology is to transform shapes generated by lithography simulation to a form that is acceptable by standard analysis tools such that electrical properties are preserved. Our approach is sufficiently fast to be run full-chip on all layers of a large design. We observe that while the difference in power and performance estimates at post-layout and on-silicon is small at ideal process conditions, it increases substantially at non-ideal process conditions. With our RET recipes, linewidths tend to decrease with defocus for most patterns. According to the proposed analyses of layouts litho-simulated at 100nm defocus, leakage increases by up to 68%, setup time improves by up to 14%, and dynamic power reduces by up to 2%. Keywords: Lithography simulation, post-OPC, analysis, verification. 1. INTRODUCTION RETs are key enablers of the aggressive IC technology scaling that has fast outpaced advancements in lithography hardware solutions. RETs such as optical proximity correction (OPC), phase shift masks (PSM), and off-axis illumination (OAI) dramatically improve resolution and are extremely effective at process variation control. The increased mask and manufacturing costs due to the application of these techniques have been outweighed by the advantages offered, and these techniques are imperative during mask-data preparation. RETs modify the design significantly and there is little similarity left with the design at the post-layout stage at which sign-off is performed. At non-ideal process conditions significant process variations can result even within the process window. Due to RETs and process variations features do not print at their nominal dimensions causing circuit power and performance to be significantly different from sign-off estimates. Today’s design flows worst-case process effects and consequently overdesign circuits leaving valuable performance on the table. Lithography simulation * enables estimation of CD variations at different process points. According to the international technology roadmap for semiconductors (ITRS), a substantial fraction of variations is systematic and can be modeled accurately after layout. 1 So even though random variations cause differences between on- silicon shapes and those predicted by lithography simulation, these difference are relatively small. Consequently, lithography simulation-based design analyses are likely to be significantly more accurate to on-silicon than post- layout analyses. Current lithography simulation tools are completely shape-based and not connected to the design in any way. In this paper we present a novel methodology that uses the results of lithography simulation Further author information: (Send correspondence to Puneet Gupta) Puneet Gupta: E-mail: puneet@blaze-dfm.com, Telephone: 1 408 470 4925 Work done by Saumil Shah and Puneet Sharma at Blaze DFM, Inc. * Residual OPC critical dimension (CD) error or post-OPC edge placement error (EPE) results can be easily used to generate an output similar to that of lithography simulation by adding the errors to the drawn CD. Design and Process Integration for Microelectronic Manufacturing IV, edited by Alfred K. K. Wong, Vivek K. Singh, Proc. of SPIE Vol. 6156, 61560T, (2006) · 0277-786X/06/$15 · doi: 10.1117/12.658129 Proc. of SPIE Vol. 6156 61560T-1