Time-Interleaved Analog-To-Digital Converters: Status and Future Directions Christian Vogel Christian Doppler Laboratory for Nonlinear Signal Processing Signal Processing and Speech Communication Laboratory Graz University of Technology, Austria Email: c.vogel@ieee.org H˚ akan Johansson Division of Electronics Systems Department of Electrical Engineering Link¨ oping University, Sweden Email: hakanj@isy.liu.se Abstract— We discuss time-interleaved analog-to-digital converters (ADCs) as a prime example of merging analog and digital signal processing. A time-interleaved ADC (TI-ADC) consists of M parallel channel ADCs that alternately take samples from the input signal, where the sampling rate can be increased by the number of channels compared to a single channel. We recall the advantages of time interleaving and investigate the problems involved. In particular, we explain the error behavior of mismatches among the channels, which distort the output signal and reduce the system performance significantly, and provide a concise framework for dealing with them. Based on this analysis, we review the principle possibilities of calibrating TI-ADCs, where we point out the necessities and advantages of digital enhancement. To this end, we discuss open issues of channel mismatch identification as well as channel mismatch correction. I. I NTRODUCTION Since analog-to-digital converters (ADCs) ultimately limit the performance of today’s communication systems, high-speed, high- resolution, and power-aware ADCs are required in order to comply with new communication standards. This also leads to an increased demand for high-speed and high-resolution sampling systems in the measurement industry [1]. Present ADC technologies work on their limits and cannot be properly pushed further, since the downscaling of IC technologies to deep sub-micron technologies makes their design even more difficult. However, the increased component density of digital circuits allows for using additional chip area with small additional costs [2]. One possibility to overcome these performance limits is to use parallelism, i.e., to split the information of the analog input signal into several parallel channels, to convert them independently, and finally to recombine them into one digital output signal. In theory, which was introduced by Papoulis’ Generalized Sampling Expansion (GSE) [3], there are many ways to split the information of the input signal. In practice, only a few parallel multi-channel sampling structures [4] have been further analyzed [5]–[7], where the time- interleaved structure is among the most promising ones for the future. The idea of a time-interleaved ADC (TI-ADC) is that each channel in a system of M parallel channels alternately takes one sample, whereas the sampling frequency of one channel does not need to fulfill the Nyquist Criterion [8]. However, when in the digital domain all samples merge into one sequence we obtain an overall sampling frequency that fulfills the Nyquist criterion. Thus, sampling with an ideal TI-ADC with M channels is equivalent to sampling with an ideal ADC with an M times higher sampling rate. The channels of a TI-ADC can be realized in different converter technologies to achieve for example high-rate and low-power ADCs [9] or high-rate and high-resolution ADCs [10]. The typical structure of a TI-ADC is shown in Fig. 1. We see the analog input signal xa(t), the M time-interleaved parallel channels, ADC M−1 MUX ADC 0 ADC 1 f s /M f s /M f s digital output y[n] analog input ADC m fs/M x a (t) ϕ =1 2π M ϕ = m 2π M ϕ =(M − 1) 2π M TI-ADC ϕ =0 2π M f s /M Fig. 1. Time-interleaved ADC (TI-ADC) with M channels. Each channel alternately takes samples at a rate fs M from the input signal xa(t). At the multiplexer (MUX), the samples from the M parallel channels are merged into one output channel running at an M times higher rate fs. and the multiplexer (MUX) to recombine the digital outputs of the channels. The conversion rate of the overall system is increased by the number of channels M. It should be noticed that each channel has to deal with the entire input signal xa(t), and, therefore, the sample-and-holds in each channel have to resolve the full input signal bandwidth. From a theoretical point of view, we can increase the sampling rate of a TI-ADC by the number of channels that work in parallel in the system. Ideally, the sampling rate would linearly scale with the number of channels; however, channel mismatches ultimately limit the performance of TI-ADCs. On the one hand, the downscaling of the IC technologies complicates the matching of the components, but, on the other hand, the increased component density allows for including additional digital components with small additional costs. Therefore, we can add digital circuits to overcome the problems of analog converter circuits [11]. TI-ADCs constitute a prime example of such merging technologies, where the technology can only be properly pushed further, when we consider digitally enhanced analog circuits. II. CHANNEL MISMATCHES Each channel ADC in a TI-ADC has technology dependent errors (e.g., integral nonlinearity errors, clock jitter) like a single-channel ADC, but due to component mismatches among the channels, ad- ditional errors, called mismatch errors, are introduced [12]. This is illustrated in Fig. 2, where we see a TI-ADC with channel mismatches and without channel mismatches for a sinusoidal input signal. For