IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 6, Ver. I (Nov - Dec. 2014), PP 62-69 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org www.iosrjournals.org 62 | Page Performance of low power Domino Circuits using pseudo dynamic buffer Rajeev Kumar 1 , Maneesh kumar Singh 2 , Vimal Kant Pandey 3 Assist. Prof. Electronics Department UCST Dehradun, UK , India 1 Assist. Prof. ECE Department DIT University, Dehradun, UK , India 2 Assist. Prof. ECE Department DIT University, Dehradun, UK , India 3 rajeevkrc@gmail.com 1 ,maneesh.kr.singh@gmail.com 2 ,vimalpandey94@gmail.com 3 Abstract: this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit for different logic function, loading condition, clock frequency and power supply. Our proposed circuit reduces power consumption and power delay product of the domino circuit as compare to other domino circuit proposed earlier. All the simulation result is carried out TSMC -0.18µm CMOS technology at 1.8V power supply. Keywords: Buffer, Dynamic circuit, Power consumption, Delay, Precharge pulse I. Introduction The rapid integration of VLSI circuit is due to the increased use of portable wireless systems with low power budget and microprocessors with higher speed. To achieve high speed and lower power consumption transistor technology and power supply must be scaled down simultaneously. As the technology scales down the threshold voltage (Vth) of the transistor also lowers in the same proportionate (Das and Brown 2005). Scaling of threshold voltage results in exponential increase of sub threshold leakage current in the evaluation transistor and makes the domino logic less noise immune. This logic family offers a number of interesting features compared to static logic, namely reduced transistor count as well as reduced load capacitance and hence improved speed. The operation of a dynamic logic gate is controlled by a clock signal and can be implemented in either Pull-up (P-type) or Pull-down (N-type) configurations [1]. The voltage at the output of the dynamic circuit is stored on a parasitic capacitance, which is typically buffered before it is sent to the next stage. This temporary voltage is affected not only by charge sharing of the internal parasitic capacitances [2], but also by the consequent dynamic circuit. Normally, a buffer at the output of the dynamic logic is required to drive the next stage. A typical domino gate [1] consists of a P-type or N-type network followed by a static inverter. But domino logic use dual phase namely precharge and evaluation to implement complex circuit with single evaluation network [3].Domino circuit has drawback of high power consumption due to clock loading and reduce noise margin due to charge sharing and charge leakage. Buffer is required to drive the output of the domino logic circuit into the next stage [4]. It is seen that static logic circuit consume power due to redundant switching at the output node. But domino logic circuit consumes power due to redundant switching at dynamic and output node [5]. This redundant switching increase the power consumption. The rest of the paper is organized as follows : In section –II previous work ,section III-Proposed Circuit Buffer, section IV-Simulation result. II. Previous Work Fang Tang at el [6], to designed pseudo dynamic buffer (PDB) for footed domino logic circuit implementation of Fig.1 and Fig.2. Fig. 1(a) & (b) shows the schematic and implementation of a conventional footed clock controlled domino logic circuit, which consists of a dynamic N-type gate (Pull-down network PDN) followed by a static inverter. The circuit operates in two phases, namely precharge and evaluation phases. During the precharge phase the clock signal clk is pulled low thus turning on the PMOS transistor M1 enabling to precharge the dynamic node Z. During the evaluation phase, the clock signal clk is pulsed high, thus turning on the NMOS transistor M2. When the input A is low, the logic at node Z is kept high regard less of the operating phase. However, when the input A is high, two phases (evaluation and precharge) should be discussed as depicted in Fig. 1(C). During the precharge phase, node Z is charged up to Vdd as well as node B. The voltage at node F drops downto„0‟, resulting in a propagation of the precharge phase to the output of the buffer. The