IJDACR ISSN: 2319-4863 International Journal of Digital Application & Contemporary research Website: www.ijdacr.com (Volume 3, Issue 2, September 2014) SNR Reduction of 2 nd Order Sigma Delta Modulator using Genetic Algorithm Monika Singh M. Tech. Scholar Electronics & Telecommunication Dept. SSTC, Bhilai (India) singh_monika30@yahoo.com Anil Kumar Sahu Assistant Professor Electronics & Telecommunication Dept. SSTC, Bhilai (India) anilsahu82@gmail.com Abstract – Over-sampling sigma-delta analog-to-digital converters (ADCs) are one of the key building blocks of state of the art wireless transceivers, especially with the voice communication system. This paper addresses a brief review for designing a Sigma-Delta modulator. A Genetic Algorithm (GA) based 2 nd order Sigma-Delta modulator design is proposed. Keywords – ADC, Genetic Algorithm, Sigma-Delta modulator, Transceiver. I. INTRODUCTION Data converters comprise a major portion of the analog circuits used in signal processing IC’s. They are found at locations in the signal chain where the signal is converted from the analog domain to digital domain, and vice versa. Because this paper focuses on the design of a Sigma-Delta (ΣΔ) modulator that would be used in an Analog-to-Digital (A/D) converter, the following section will provide a survey of common A/D architectures, some fundamental ΣΔ A/D concepts, common performance metrics, and some current trends in ΣΔ A/D design. II. ANALOG-TO-DIGITAL (A/D) ARCHITECTURES Many A/D conversion schemes have been proposed and implemented. The ideal A/D converter would be fast and accurate, but unfortunately these performance metrics are contradictive. Thus, the topic of A/D conversion encompasses many designs that offer some compromise between these two qualities. Table 1 presented in [1] compares many of the common A/D converter architectures on the basis of accuracy and speed. Table 1: Survey of A/D Converter Architectures [1] Low-to-Medium Speed, High Accuracy Medium Speed, Medium Accuracy High speed, Low-to-Medium Accuracy Integrating Successive Approximation Flash - Algorithmic Two-step - - Interpolating - - Folding - - Pipelined - - Time-Interleaved As noted in the table ΣΔ converters are typically classified as low-to-medium speed, high accuracy data converters. ΣΔ modulator could be used in a high speed, medium accuracy A/D converter. Thus, the design will broaden the current definition of ΣΔ A/D converters, and allow them to compete with some of the higher speed architectures. ΣΔ Modulation ΣΔ A/D converters use oversampling of the input signal and noise shaping to achieve their performance. Oversampling implies that the input signal is captured at a rate higher than the Nyquist rate. A common parameter used for ΣΔ converters is the oversampling ratio (OSR), defined as:  = ௙  ௙  (1) Where   is the sampling frequency and  ௬௚ is the Nyquist frequency, defined as a frequency twice the highest frequency component of the input. By oversampling the input signal, the quantization error which is the artifact of the conversion from analog to digital, is spread over a larger range of frequencies. The result is a 3dB increase in the dynamic range every time the sampling frequency is doubled [1]. The other property common to ΣΔ converters is noise- shaping, accomplished with the ΣΔ modulator. Figure 1: Linear model of a ΣΔ modulator Figure 1 illustrates a linearized z-domain model of a ΣΔ modulator. The model assumes that the quantization error can be modelled as additive white noise, with properties that that ሺݖሻ ݔሺሻ ሺሻ ݕሺሻ ݑሺሻ