REF : 2014/ III/ ....... SESSION OF NOVEMBER 2014 Ministry of Higher Education and Scientiļ¬c Research of Tunisia University of La Manouba National School of Computer Science ENSI A THESIS PRESENTED IN VIEW OF THE OBTENTION OF ENGINNERING DEGREE IN COMPUTER SCIENCE AUTOMATED FRAMEWORK FOR POWER, DELAY AND AREA OPTIMIZATION IN VERILOG CIRCUIT AUTHOR :YASSINE MAALEJ S UPERVISOR : Prof. Kyusun Choi Director of Chip Lab Pennsylvania State University ADVISOR : Prof. Sadok Bouamama Professor at ENSI Academic Year : 2013 - 2014