[M.Vijayan 4(2): February,2015] ISSN: 2277-9655 Scientific Journal Impact Factor: 3.449 (ISRA), Impact Factor: 2.114 http: // www.ijesrt.com © International Journal of Engineering Sciences & Research Technology [96] IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY RECENT TREND BASED WALLACE TREE MULTIPLIER AIMING TO LOW LEAKAGE POWER M.Vijayan*, T.Jayachandran, D.Arulanantham * ECE Department,Velalar College of Engineering and technology,India ECE Department,Nandha Engineering College,India ECE Department,Nandha Engineering College,India ABSTRACT A new domino circuit is proposed with low leakage and high noise immunity which decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper for wide fan-in gates to implement fast and robust circuits. The technique utilized is based on comparison of mirrored current of the pull-up network with its worst case leakage current. Thus, the power consumption and delay are reduced. A 4*4 Wallace tree multiplier is designed based on CCD (Current Comparison Domino) which uses low leakage high speed full adders. These full adders uses current comparison based domino logic to achieve low leakage and high speed. The proposed 4*4 Wallace tree multiplier using current comparison based domino logic full adders was simulated using 180nm CMOS technology which shows a relative power reduction when compared to the 4*4 Wallace tree multiplier using standard full adders. KEYWORDS: Domino logic, Leakage-tolerant, Noise immunity, Wallace Multiplier, Wide fan-in. INTRODUCTION Dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic circuits. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed. In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven. Dynamic logic, when properly designed, can be over twice as fast as static logic. It uses only the faster N transistors, which improve transistor sizing optimizations. Static logic is slower because it has twice the capacitive loading, higher thresholds, and uses slow P transistors for logic. Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed. In Dynamic logic, problem arises when cascading one gate to the next. In order to cascade dynamic logic gates, one solution is Domino Logic, which inserts an ordinary static inverter between stages. While this might seem to defeat the point of dynamic logic, since the inverter has a pFET, there are two reasons it works well. First, there is no fanout to multiple pFETs. The dynamic gate connects to exactly one inverter, so the gate is still very fast. And since the inverter connects to only nFETs in dynamic logic gates, it too is very fast. Second, the pFET in an inverter can be made smaller than in some types of logic gates. In this paper, a new current-comparison-based domino (CCD) [1] circuit for wide fan-in applications in ultradeep submicrometer technologies is proposed. The novelty of the proposed circuit is that our work simultaneously increases performance and decreases leakage power consumption. With this, a low leakage Wallace tree multiplier [2] is designed to show its minimum power consumption. The rest of this paper is arranged as follows. After the existing system in Section II, the proposed circuit is described in Section III. Section IV includes simulation results for the proposed circuit using 180nm CMOS tool compared with other conventional circuits. Section V concludes the results.