Exploring Design Space of 3D NVM and eDRAM Caches Using DESTINY Tool Sparsh Mittal ⋆ , Matt Poremba ¶ , Jeffrey S. Vetter ⋆§ , Yuan Xie ♯ ⋆ Oak Ridge National Laboratory ¶ Pennsylvania State University § Georgia Institute of Technology ♯ University of California at Santa Barbara Email: mittals@ornl.gov,mrp5060@psu.edu,vetter@ornl.gov,yuanxie@ece.ucsb.edu Abstract—To enable the design of large sized caches, novel memory technologies (such as non-volatile memory) and novel fabrication approaches (e.g. 3D stacking) have been explored. The existing modeling tools, however, cover only few memory tech- nologies, CMOS technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 3D (and 2D) cache designs using SRAM, embedded DRAM (eDRAM), spin transfer torque RAM (STT-RAM), resistive RAM (ReRAM) and phase change RAM (PCM). DESTINY is very useful for performing design-space exploration across several dimensions, such as op- timizing for a target (e.g. latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e. 2D v/s 3D) for a given optimization target etc. DESTINY has been validated against several cache prototypes. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. Keywords—Cache, SRAM, eDRAM, non-volatile memory (NVM or NVRAM), STT-RAM, ReRAM, PCM, modeling tool, emerging memory technologies, validation. I. I NTRODUCTION Due to recent trends of increasing system core-count and memory bandwidth bottleneck, processor designers are us- ing large size on-chip caches. For example, Intel’s Ivytown processor has 37.5MB SRAM LLC [2]. To overcome the limitations of SRAM, such as high leakage power consumption and low density, researchers have explored alternate memory technologies, such as eDRAM, STT-RAM, ReRAM and PCM [3, 4]. These memory technologies enable design of large size caches, for example, Intel’s 22nm Haswell processor employs 128MB L4 eDRAM cache [5]. Researchers are also explor- ing novel fabrication techniques such as 3D integration that enables vertical stacking of multiple layers [6]. 3D stacking offers several benefits such as high density, higher flexibility in routing signals, power and clock and ability to integrate diverse memory technologies for designing hybrid caches. Lack of open-source, comprehensive and validated model- ing tools, however, presents a bottleneck in full study of emerg- ing memory technologies and design approaches. Although a Sparsh Mittal and Matt Poremba are co-first authors. This ORNL technical report number ORNL/TM-2014/636 is an extension of our paper [1] accepted in DATE (Design, Automation and Test in Europe) conference, to be held between 9-13 March, 2015. The specific extensions made in this report are listed at the end of Section 1. few modeling tools exist, they model only a subset of memory technologies, for example NVSim [7] models only 2D designs of SRAM and NVMs but not eDRAM. As an increasing number of industrial designs utilize 3D stacking [8, 9], research on 3D stacking has become even more important. Existing 3D modeling tools such as CACTI-3DD [10] and 3DCacti [11] do not model NVMs. Further, different tools use different assumptions and modeling frameworks, and hence, comparing the estimates obtained from different tools may be incorrect. Also, tools such as 3DCacti are not capable of modeling of recent technology nodes (e.g. 32nm). It is clear that a single, validated tool which can model both 2D and 3D designs using prominent memory technologies is lacking. In absence of such a tool, several architecture-level studies on 3D caches (e.g. [12]) derive their parameters using a linear extrapolation of 2D parameters which may be sub-optimal or even inaccurate. A. Contributions In this paper, we present DESTINY 1 , a 3D de sign-s pace explorati on tool for SRAM, eDRAM and n on-volatile memory . DESTINY utilizes the 2D circuit-level modeling framework of NVSim tool for SRAM and NVMs. It also utilizes the coarse- and fine-grained TSV (through silicon via) models from CACTI-3DD tool. Further, DESTINY adds the model of eDRAM (Section III-A) and two additional types of 3D de- signs (Section III-B). Overall, DESTINY enables modeling of both 2D and 3D designs of five memory technologies (SRAM, eDRAM and three NVMs), which includes both volatile and non-volatile memories. Also, it can model technology nodes ranging from 22nm to 180nm. Finally, by virtue of being an open-source tool, it facilitates reproducible research and easy extension of the tool for many more usage scenarios than that discussed in the paper. We have compared the results obtained from DESTINY against several commercial prototypes [8, 9, 13–17] to validate 2D design of eDRAM and 3D designs of SRAM, eDRAM and ReRAM in DESTINY (Section IV). The modeling error has been observed to be less than 10% for most cases and less than 20% for all cases. This can be accepted as reasonable for an academic modeling tool and is also in range with the errors produced by previous tools [7]. 1 The source-code of DESTINY can be cloned from the following git repository: https://code.ornl.gov/3d cache modeling tool/destiny.git