IJRECE VOL. 3 ISSUE 1 JAN-MAR 2015 ISSN: 2393-9028 (PRINT) | ISSN: 2348-2281 (ONLINE) INTERNATIONAL JOURNAL OF RESEARCH IN ELECTRONICS AND COMPUTER ENGINEERING A UNIT OF I2OR 41 | Page Implementation of 64 Bit KoggeStone Carry Select Adder with BEC for Efficient Area B.Tapasvi 1 , K.Bala Sinduri 2 , I.Chaitanya Varma 3 , N .Udaya Kumar 4 1 M.Tech Student, Department of ECE, SRKR Engineering College, Bhimavaram, India 2 Assistant Professor, Department of ECE, SRKR Engineering College, Bhimavaram, India 3 B.Tech Student, Department of ECE, SRKR Engineering College, Bhimavaram, India 4 Professor, Department of ECE, SRKR Engineering College, Bhimavaram, India Abstract— Carry Select Adder (CSLA) is one of the faster adder used in many data-processing processors to perform fast arithmetic functions. The speed of operation of such an adder is limited by carry propagation from input to output. This paper discusses about the implementation of linear Carry Select Adder with Kogge Stone Adder. The Kogge Stone parallel approach will give option to generate fast carry for intermediate stages. From the structure of line- ar CSLA it is clear that there is scope for reducing the area in CSLA by using Binary to Excess 1 converter. 64 bit line- ar CSLA architecture with Kogge stone is implemented which reduces area with slight increase in delay when com- pared with Regular Linear 64 bit CSLA architecture. Simu- lation and Synthesis are carried on Modelsim 6.3 and Xilinx ISE 12.2. Keywords—Kogge Stone Adder (KSA), Binary to excess- 1 Converter (BEC),Carry Select Adder(CSLA).Ripple Carry Adder (RCA),Regular Carry Select Adder(RCSLA). I. INTRODUCTION Binary addition is the most fundamental arithmetic oper- ation. It has been ranked the most extensively used opera- tion among a set of real-time digital signal processing benchmarks from application-specific DSP processors to general-purpose processors. In particular, carry-propagation adder (CPA) is frequently part of the critical delay path lim- iting the overall system performance due to the inevitable carry propagation chain. The speed of addition is limited by the time required to propagate a carry through the adder. The CSLA is used in many computational systems to mod- erate the problem of carry propagation delay which com- promises between RCA and CSLA. The CSLA requires dual RCAs in which RCA with "cin=1" replaced by BEC improves area. The CSLA using variable block sizing, the delay can be further reduced. To increase the speed of CSLA, parallel prefix adder is used instead of RCA. The kogge-stone adder has low critical path and maximum fan- out. The high speed regular and modified CSLA is designed using kogge-stone adder by replacing RCA with "cin=0". The details of ripple carry adder, multiplexer, binary to excess -1 converter and carry select adder discussed in Sec- tion II, the complete functioning of Kogge-Stone Adder is discussed in section III, The implementation of High Speed Proposed CSLA architectures in Uniform and Variable block size is described in section IV and V. The perfor- mance and simulation results are presented and discussed in section VI. The CSLA is used in many computational systems de- sign to moderate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. It uses independent ripple carry adders (for Cin=0 and Cin=1) to generate the resultant sum. However, the Regular CSLA (RCSLA) is not area and speed efficient because it uses multiple pairs of Kogge Stone Adders (KSA) to generate partial sum and carry by considering carry input. The final sum and carry are selected by the multiplexers (mux). Due to the use of two independ- ent KSA the area will increase which leads an increase in delay. To overcome the above problem, the basic idea of the proposed work is to use n-bit binary to excess-1 code con- verters (BEC) to improve the speed of addition [1]. This logic can be replaced in KSA for "Cin=1" to further im- proves the speed and thus reduces the delay. Using Binary to Excess-1 Converter (BEC) instead of KSA in the RCSLA will achieve lower area, delay which speeds up the addition operation of Modified CSLA (MCSLA). The main ad- vantage of this BEC logic comes from the lesser number of logic gates than the Full Adder (FA) structure because the number of gates used will be decreased. Ripple Carry Adder consists of cascaded “N” si ngle bit full adders. Output carry of previous adder becomes the input carry of next full adder. Therefore, the carry of this adder traverses longest path called worst case delay path through N stages. Now as the value of N increases, delay of adder will also increase in a linear way. Therefore, RCA has the lowest speed amongst all the adders because of large propagation delay but it occupies the least area. Parallel prefix adders can also be used to reduce the delay. Several examples of such adders have been published and there are many efficient implementations. Kogge and Stone scheme limit the lateral logical fan-out at each node to unity, but at the cost of a dramatic increase in the number of lateral wire at each level. II. BINARY TO EXCESS-1 CONVERTER The basic work is to use Binary to Excess-1 Converter (BEC) in the regular CSLA to achieve lower area and in- creased speed of operation. This logic is replaced in KSA with "Cin=1". This logic can be implemented for different bits which are used in the modified design. The main ad- vantage of this BEC logic comes from the fact that it uses lesser number of logic gates than the n-bit Full Adder (FA)