[Hiremath, 4(2): February, Year] ISSN: 2277-9655 Scientific Journal Impact Factor: 3.449 (ISRA), Impact Factor: 2.114 http: // www.ijesrt.com© International Journal of Engineering Sciences & Research Technology [359] IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY DESIGN AND IMPLEMENTATION OF SERIAL DIVIDER USING 180NM PROCESS TECHNOLOGY Yogita Hiremath * , Akalpita L. Kulkarni, Dr. J. S. Baligar * PG student, ECE Dept., Dr. AIT, Bangalore, India Associate Professor, ECE Dept., Dr. AIT, Bangalore, India Associate Professor, ECE Dept., Dr. AIT, Bangalore, India ABSTRACT This paper presents an efficient 4-bit unsigned binary serial divider and its implementation using 180nm CMOS process technology. The layout design of the serial divider circuit is efficiently optimized in terms of area. The serial divider circuit provides a good compromise between area and performance in divider design. The serial divider is designed based on repeated one’s complement binary subtraction algorithm. The implementation consists of several combinational and sequential components such as 4-bit ripple carry adder, 2:1 multiplexers, D flip-flops and 4-bit synchronous up counter. The circuit analysis is carried out in terms of performance parameters such as transistor count, propagation delay and power consumption. According to the estimations done, the transistor count, propagation delay and power consumption of the serial divider without parasitics was found to be 568, 5.13ns and 196.2μW respectively.The presence of parasitics due to metal layers in the layout design increase propagation delay to 86.42ns and power consumption to 206μW. Keywords: Area, Cadence, Layout, Power consumption, Propagation Delay, Parasitics. INTRODUCTION Technology scaling of transistor feature size has provided a remarkable innovation in silicon industry for the last three decades. Designers are striving for small silicon area, higher speeds, low power consumption and reliability due to ever increasing demand and popularity of portable electronics. Circuit realization for low power and low area has become an important issue with the growth of integrated circuit towards very high integration density and high operating frequencies. The advances in VLSI technology, more and more functionality complexity have been integrated into digital designs to better support target applications. With many applications requiring support for arithmetic units, complex arithmetic modules like multipliers and dividers are now being extensively used in design. Of all the elemental operations, division is the most complicated operation and can consume the most resources (in either silicon, to implement the algorithm in hardware or in time, to implement the algorithm in software). Binary division operation is of immense importance in the field of engineering science. Inherently, division operation is a sequential type of operation, thereby it is more costly in terms of computational complexity and latency (propagation delay) compared with other mathematical operations. It is of little surprise that, an efficient division algorithm can considerably improve the performance of the ALU component of any digital circuit. In other words, an efficient division algorithm is one of the main aims of a designer while implementing an ALU circuit. Many division algorithms have been presented such as division by means of repeated subtraction, division based on successive approximation of quotient and carry free division algorithm. Binary divider can be categorized in two types, serial divider and parallel divider. The operation of division in serial divider is done by means of repeated subtraction. Suppose we want to divide 19 by 3. So we repeatedly subtract 3 from 19 and after six times subtraction, remainder is one, so less than divisor, so further subtraction is stopped. So the quotient comes out as six and the remainder is one. Binary division is done in the same way. The proposed 4-bit binary serial divider is implemented using Cadence EDA tool [1]. The tool provides sophisticated features such as Cadence Virtuoso schematic editor which provides sophisticated capabilities which speed and ease the design, Cadence Virtuoso Visualization and Analysis which efficiently analyzes the performance of the design, Cadence Virtuoso Layout Suite that speeds up the physical layout of the design and Cadence Assura Physical Verification reduces overall verification time