International Journal of Scientific and Research Publications, Volume 4, Issue 3, March 2014 1 ISSN 2250-3153 www.ijsrp.org LOW-POWER AND LOW-AREA ADAPTIVE FIR FILTER BASED ON DISTRIBUTED ARITHMETIC AND LMS ALGORITHM K.JEBIN ROY*, R.RAMYA** *M.E. VLSI Design, Department of ECE, Anand Institute of Higher Technology, Chennai-603103, India **M.Tech. VLSI Design, Department of ECE, Sathyabama University, Chennai-600119, India Abstract- In this manuscript, an unusual adaptive FIR filter using distributed arithmetic (DA) for area efficient design is implemented. DA is bit-serial computational action and uses parallel look-up table (LUTs) apprise and equivalent implementation of filtering and weight-update operations to appliance high throughput filter rates irrespective of the filter length. The full adder based conditional signed carry save accumulation for DA-based inner product computation is swapped and design by using 10 transistor full adder based carry save accumulation of shift accumulation, with the intention of the proposed design, it can reduce the area complexity and power consumption. The least-mean-square (LMS) algorithm adaptation is functioned to update the weight and abate the mean square error between the assessed and chosen output. The weight increment block based adder/subtractor cells is exchanged by carry save adder in order to reduce area difficulty. It comprises of multiplexors, smaller LUT, and practically half the number of adders contrasted to the present DA-based design. Index Terms: Adaptive Filter, Distributed Arithmetic (DA), Finite Impulse Response (FIR), Least Mean Square (LMS) Algorithm, Lookup table (LUT). I. INTRODUCTION Adaptive filters find extensive use in many signal processing applications such as channel equalization, echo cancellation, noise cancellation [1]. The finite impulse response (FIR) filters whose weights are updated by the famous Widrow-Hoff least mean square (LMS) algorithm is the most popularly used adaptive filter not only due to its simplicity but also due to its satisfactory convergence performance [5]. The direct form configuration on the onward path of the FIR filter results in a long critical path due to an inner product computation to obtain a filter output. Consequently, it is required to reduce the critical path of the structure if the input signal has high sampling rate. By reducing the critical path of the structure, thereby, the critical path could not exceed the sampling period. Distributed arithmetic (DA) is so named because it performed arithmetic operation. DA is bit serial computation in nature and it eliminates the need for hardware multipliers and is capable of implementing large order filters with very high throughput. A lot of study has been done to implement the DA based adaptive FIR filter for area efficient design, the multiplier-less distributed arithmetic (DA) based technique has achieved plenteous popularity for its high throughput, but it results are increased in cost-effective, area and time efficient computing structures [8]. DA based hardware efficient adaptive FIR filter inner product has been suggested by Allred et al. [2] using two separate lookup tables (LUTs) Filtering lookup table and Auxiliary lookup table for filtering and weight updating module. Later, Guo and DeBrunner [3], [4] have improved the design structure in [2] by using only one lookup table instead of two LUTs for both filter and weight updating module. On the other hand, the design process in [2], [3], [4] and [8] require more cycles for lookup table (LUT) update for each new sample, hence it do not support high sampling rate. Meher and Park have improved the design with low adaptation delay for high speed DA based adaptive filter [6]. In a recent paper, Meher and Park proposed a new DA based adaptive filter architecture for low power, low area and high throughput with very low adaptation delay [7]. This brief proposes an adaptive FIR filter using distributed arithmetic for area efficient design. High Throughput is achieved by using a parallel lookup table update and equivalent implementation of filtering and weight-updating operations. The conditional signed carry saved accumulation for DA-based inner product computation is designed by using 10 transistor full adder based carry saved accumulation of shift accumulation. The use of the proposed design helps to reduce the area complexity and power consumption. In the next section, a brief study of the least mean square (LMS) adaptive algorithm, followed by the description of the proposed DA based technique filter in Section III. The structure of the proposed adaptive filter and description of the proposed DA based adaptive FIR filter in Section IV. Results and Conclusions are given in Section V and VI. II. Review of LMS Adaptive Algorithm The LMS algorithm computes a filter output and an error value that is equal to the difference between the current filter output and the desired response for every clock cycle. In every training cycle, the estimated error is then used to update the filter weights. The weights of LMS adaptive filter during the nth iteration is updated according to the following equations [6]: ሺ  ሻ  ሺሻ    ሺሻ  ሺሻ (1a) Where ሺሻ  ሺሻ  ሺሻ (1b) ሺሻ    ሺሻ  ሺሻ (1c)