Volume IV, Issue II, February 2015 IJLTEMAS ISSN 2278 - 2540 www.ijltemas.in Page 68 Bio-Inspired Ultra Low Power Design of Op-amp with Input Compensation for Biomedical Application (Pacemaker) Jubin Jain 1 , Vijendra Maurya 2 , Anu Mehra 3 1 Department of Electronics & Communication Engineering , Geetanjali Institute of Technical Studies,Udaipur 2 Department of Electronics & Communication Engineering , Geetanjali Institute of Technical Studies,Udaipur 3 Department of Electronics & Communication Engineering , ASET Amity University, Noida Abstract: Due to the rising trends of technologies which are highly inclined towards the low voltage & low power consumption of silicon chip devices which are being developing exponentially due to the rising demand of smaller sized devices which are needed to be operated at lower voltage so that it can support longer battery life which can be used in portable applications such as in marketing segments including telecommunications, biomedical, computers and consumer electronics. It has become major concern that while designing any chip, power consumption is required to be kept in mind especially when it is concerned to biomedical devices. The supply voltage is being scaled down to reduce overall power consumption of the system. The objective of this project is to design ultra low powered operational amplifier which is operated at lower voltage 1.8V. As the voltage is lowered some of the parameters are sacrificed but still it is tried to satisfy the major parameters .It is also not possible to reduce the size of battery upto certain extent due to some chemical limitations, so a pathway is proposed to make the architectural changes. This project showcase the operational amplifier schematic implementation, simulation results with the 0.18μm technology designed in Tanner EDA 14.1. The operational amplifier is used to implement the ADC circuit. The op-amp specially designed for biomedical application (Pacemaker) on an account to improve the battery life of pacemaker. The Project will briefly showcase the performance parameter of OPAMP with compensation at input. Keywords: Power consumption, SNR, Trans-conductance compensation stage, OTA. I. INTRODUCTION everal improvements have been done in processing which has pushed the scaling of device dimensions persistently over the past years. The driving force behind this trend is to reduce IC production cost since more components on a chip are possible. In addition to device scaling, the rise in the portable electronics market is also encouraging functioning of device at low voltage and low power circuitry since this would reduce battery size and weight and would enable longer battery life time. The Operational Amplifier (Op-Amp) is undoubtedly one of the most useful devices in analog electronic circuitry. While designing an op-amp, various electrical characteristics are required to be considered e.g. gain bandwidth, slew rate, common mode range, output swing, offset, power dissipation. Power dissipation of the circuit depends on three parameters frequency, supply voltage and capacitance. If the supply voltage is reduced power consumption can be reduced. But as we keep on decreasing the supply voltage, it also becomes very difficult to drive transistors in saturation region. On an account to achieve the required degree of stability, which is determined by phase margin, other performance parameters are usually compromised. As a result, designing an op-amp must meet all specifications such that it is needed that a good compensation strategy has to be proposed. A. Operational Amplifier An operational amplifier (Op-Amp) is a DC coupled input voltage amplifier with high gain. Which is capable of an output voltage a million times greater than the voltage difference across its two input terminals. Fig.1. Block Diagram of OPAMP 1. The first block is input differential amplifier, which is responsible for providing very high input impedance, a large CMRR and PSRR, high gain, a low offset voltage, and low noise. 2. The second stage performs Level shifting, added gain and differential to single ended converter. 3. The third block is the output buffer. The output buffer sometimes may be replaced form a high output resistance S