International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-1, March 2012 438 FPGA Implementation On Reversible Floating Point Multiplier M.Jenath, V.Nagarajan Abstract-Field programmable gate arrays (FPGA) are increasingly being used in the high performance and scientific computing community to implement floating-point based system. The reversible single precision floating point multiplier (RSPFPM) requires the design of reversible integer multiplier (2424) based on operand decomposition approach. Reversible logic is used to reduce the power dissipation than classical logic and do not loss the information bit which finds application in low power computing, quantum computing, optical computing, and other emerging computing technologies. Among the reversible logic gates, Peres gate is utilized to design the multiplier since it has lower quantum cost. Operands of the multiplier is decomposed into three partitions of 8 bits each using operand decomposition method. Thus the 2424 bit reversible multiplication is performed through nine reversible 8x8 bit multipliers and output is summed to yield an efficient multiplier optimized in terms of quantum cost, delay, and garbage outputs. This proposed work is designed and developed in the VHSIC hardware description language (VHDL) code and simulation is done using Xilinx 9.1simulation tool. Key words: Reversible logic gates, reversible logic circuits, reversible multiplier circuits, quantum computing, Nanotechnology based systems. I. INTRODUCTION In VLSI circuit design, reduction of power dissipation is the one of the major goal. As demonstrated by R.Landauer in the early 1960s, irreversible hardware computation, regardless of its realization techniques, results in energy dissipation due to the information loss [1]. It is proved that the loss of each one bit of information dissipates at least KTln2 joules of energy(heat), where K=1.3806505x10 -23 m 2 kg -2 K -1 (joules Kelvin-1) is the Boltzmann‟s constant and T is the absolute temperature[1]. Manuscript received January 09, 2012. M.Jenath, Department of Electronics and Communication Engineering, Anna university of Technology. Adhiparasakthi Engineering College, Melmaruvathur, Chennai, India (jenath.mohamad @gmail.com ) *Dr.V.Nagarajan, Department of Electronics and Communication Engineering, Anna university of Technology. Adhiparasakthi Engineering College, Melmaruvathur, Chennai, India (nagarajanece31@rediffmail.com) Reversible logic circuits have theoretically zero internal power dissipation because they do not lose information. Hence, In 1973, Bennett showed that in order to avoid KTln2 joules of energy dissipation in a circuit, it must be built using reversible logic gates [2].A circuit is said to be reversible if the input vector can be uniquely recovered from the output vector and there is a one-to-one correspondence between its input and output assignments, i.e. not only the outputs can be uniquely determined from the inputs, but also the inputs can be recovered from the outputs .Thus the number of inputs and outputs in reversible logic gates or circuits are equal. Reversible logic has received great attention in the recent years due to their ability to reduce the power dissipation which is the main requirement in low power Very large scale integration (VLSI) design. Quantum computers are constructed using reversible logic circuits. It has applications in various research areas such as low power CMOS design, optical computing, DNA computing, quantum computing, nanotechnology bioinformatic and thermodynamic technology. It is not possible to construct quantum circuits without reversible logic gates. Synthesis of reversible logic circuits is significantly more complicated than traditional irreversible logic circuits because in a reversible logic circuit, fan-out and feedback is not allowed. Thapliyal and Srinivas proposed the TSG gate, in reversible circuit designing. The construction of such new gates does not make any significance to reduce quantum cost nor the gate complexity[3]. Mohammadi et al (2009) has proposed a new reversible (44) multiplier circuit using “HNG” gate which has minimised the quantum cost with previous design. Michael Nachtigale et al (2010) proposed the single precision floating point multiplier (32 32) multiplier by using both Toffoli and Peres gate. This design uses the reversible 4:2 compressor and reversible Wallace tree multiplier.This reversible design of the 8x8 bit Wallace tree multiplier has been optimized in terms of quantum cost, delay, and number of garbage output [7]. Multiplication is a heavily used arithmetic operation in many computational units. It is necessary for the processors to have high speed multipliers with less hardware complexity. Floating point numbers are one possible way of representing real numbers in binary format. The IEEE 754 standard presents two different floating point formats, Binary interchange format and Decimal interchange format. Multiplying floating point numbers is a critical requirement for DSP applications involving large dynamic range. This paper focuses only on single precision binary interchange format. The proposed system describes a reversible single precision