Advancement in Energy Efficient Routing Algorithms for 3-D Network-on-Chip Architecture Abdul Quaiyum Ansari 1 , Mohammad Ayoub Khan 2 and Mohammad Rashid Ansari 3 1,3 Department of Electrical Engineering, Faculty of Engineering and Technology, Jamia Millia Islamia, New Delhi 2 Department of Computer Science, Faculty of Engineering and Technology, Sharda University, Gr. Noida E-mail: 1 aqansari@ieee.org, 2 ayoub@ieee.org, 3 rashid.vns@gmail.com ABSTRACT For adapting to the present and future requirements of electronic systems, integration of 3-D technology is very promising. 3-D Network-on-Chip design enhances execution rate and decreases power utilization by replacing long flat interconnects with short vertical ones. To attain higher execution speed along with reduced energy consumption can be obtained by optimizing routing algorithms. This paper explores the various routing algorithms used in 3D NoC. The main objective of this survey is to provide the latest information about routing algorithms for various 3-D NoC used to reduce the power consumption. Keywords: 3D NoC, Routing Algorithm INTRODUCTION As the number of Processing Elements (PE) are increasing in a 2D Multiprocessor System-on-Chip (SoC), the performance is reduced because of increased in average interconnect length [1]. This design constraint of SoC is addressed effectively by 3-D NoC. Various challenges and issues that have now been well understood and solved for 2-D, are required to be restudied in 3-D IC systems design. Analogous to multi-storey buildings coming into the densely packed and populated metropolitan cities, three-dimensional integration chip structures can be imagined as an answer for soaring transistor densities and burgeoning die size in multi-level and multi-core architecture. The recent inclination towards 3-D chip designing has been mainly motivated by following factors, firstly because of increase in number of on-chip processing cores and memories– instigated by the explosion in transistor densities- has put tremendous strain on off-chip memory bandwidth and therefore, designers have to look for the third dimension to increase the number of links arriving at a specific core. By adding potentially two additional gateways to the on-chip cores (one from above and one from below), architects can imagine systems with enough memory bandwidth to take benefit of the extensive multi-core revolution. Second reason is that because the modern SoC contains mixed-signal technology, such as digital to analog converters, wireless transceivers integrated with digital systems, traditionally analog and digital components were implemented in different chips and then integrated on one board, but, 3D chip 104