ISSN (Print) : 2320 – 3765 ISSN (Online): 2278 – 8875 International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering Vol. 2, Issue 7, July 2013 Copyright to IJAREEIE www.ijareeie.com 3317 VHDL Implementation of Non Restoring Division Algorithm Using High Speed Adder/Subtractor Sukhmeet Kaur 1 , Suman 2 , Manpreet Singh Manna 3, Rajeev Agarwal 4 M.Tech Student, ECE, SSIET, Derabassi, Punjab, India 1 Asst. Professor, ECE, SSIET, Derabassi, Punjab, India 2 Associate Professor, EIE, SLIET (Deemed University) Longowal, Sangrur, India 3 Assistant Professor, ECE, SGIT Ghaziabad, U.P. India 4 ABSTRACT: Binary division is basically a procedure to determine how many times the divisor D divides the dividend B thus resulting in the quotient Q. At each step in the process the divisor D either divides B into a group of bits or it does not. The divisor divides a group of bits when the divisor has a value less than or equal to the value of those bits. Therefore, the quotient is either 1 or 0. The division algorithm performs either an addition or subtraction based on the signs of the divisor and the partial remainder. There are number of binary division algorithm like Digit Recurrence Algorithm restoring, non-restoring and SRT Division (Sweeney, Robertson, and Tocher), Multiplicative Algorithm, Approximation Algorithms, CORDIC Algorithm and Continued Product Algorithm. This paper focus on the digit recurrence non restoring division algorithm, Non restoring division algorithm is designed using high speed subtractor and adder. High speed adder and subtractor are used to speed up the operation of division. Designing of this division algorithm is done by using VHDL and simulated using Xilinx ISE 8.1i software has been used and implemented on FPGA xc3s100e-5vq100. Keywords: Restoring division algorithm, Non-restoring division algorithm, high speed adder, high speed subtractor I.INTRODUCTION Computers have evolved rapidly since their creation. However, there is one thing that has not changed: The main purpose of computers is to do the arithmetic to run programs and applications. Basically, computers handle lots of numbers based on the three basic arithmetic operations of addition, multiplication and division. Compared to addition and multiplication, division is the least used operation. However, computers will experience performance degradation if division is ignored [I, 2, 3]. A survey by Oberman and Flynn [9] presents the main algorithms used for implementing division in hardware. There are three main classes for hardware-oriented division algorithms: digit recurrenc, functional iteration and table based methods. Each method has its own advantages [I], however digit recurrence division is most common algorithm for division and square root in many floating point units, since it is simple and lower in complexity than division by convergence [2, 4, 5]. Restoring, non-restoring and SRT dividers are representative algorithms for digit recurrence division. Division is equivalent to repeat subtraction of the divisor from the dividend until the quantity left is smaller in magnitude than the divisor. The number of subtractions is the quotient, and the quantity left is the remainder. This process, if done straight forwardly, is very time consuming. It is substantially speeded if the most significant digits of the divisor and dividend are aligned before the first subtraction, and the divisor then shifted to the right one position whenever the partial remainder become smaller than the divisor before shifting. One shift may be necessary before any subtraction, if the initial alignment makes the divisor larger than the dividend" In binary, at most one subtraction can be made between shifts except as noted below. Two conventional techniques avoid the need to compare the remainder with the divisor after every subtraction. In restoring division, subtraction continues until the sign of the partial remainder changes; the change causes an immediate addition of the divisor and a corresponding decrement of the accumulating quotient, before the right shift. In non restoring division, the sign change causes a shift followed by one or more additions until the sign changes back. II.RESTORING DIVISION In the restoring division method the quotient is represented using a non-redundant number system This is the “paper- and-pencil” usual algorithm. Its main characteristic is the full width comparisons required to deduce the new quotient digit[6]. In restoring division, the divisor is shift-positioned and subtracted from the dividend. If subtraction of the divisor produces a negative result at any bit position relative to the dividend, the operation at that bit position is