2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 978-1-4799-5412-4/14/$31.00 ©2014 IEEE Optimization on Cell-library Design for Digital Application Specific Printed Electronics Circuits Manuel Llamas, Mohammad Mashayekhi and Jordi Carrabina CAIAC Group Universitat Autònoma de Barcelona Campus UAB, Bellaterra 08193, Spain E-mail: name.surname@uab.cat Jody Matos and André Reis Instituto de Informática UFRGS – Universidade Federal do Rio Grande do Sul Porto Alegre 15064, Brazil E-mail: name.surname@inf.ufrgs.br Abstract—This paper presents an investigation about the ideal composition of cell libraries to be used for digital Application Specific Printed Electronics Circuits (ASPECs). Printed/organic/flexible electronics is becoming more and more important over the last years, and it seems that the industry will continue growing as new possible applications arise, and the existing ones are being improved due to better designs and fabrication processes, even moving towards integrating logic circuitry together with sensors and actuators. This paper presents considerations for developing (ASPECs), trying to keep a similar approach to the typical ASIC procedures. The work presented herein adopted a cell-based design methodology addressed to printed electronics (PE) designs. Such methodology allows us to propose a design flow for PE similar to the VLSI design flow, comprising logic synthesis, mapping, placement, and routing. In order to evaluate different library compositions, a set of benchmark has been mapped with six different combinations of mapping tools and associated libraries. The obtained results show that a simple library composed of just three cells – either NAND2, NOR2 and inverters or NAND, NAND3 and inverters – performs very well in terms of transistor count. NAND gates are usually preferred options for ratioed PMOS-only design styles. Using a more complex cell library can produce reductions of around 25% in terms of transistor count, but produce increases of around 23% as well. Keywords—ASIC; ASPEC; OTFT; Standard Cell; transistor count; logic synthesis; technology mapping; Printed Electronics. I. INTRODUCTION In last decades, the fusion of three technological areas – microelectronics, chemistry and printing – has create a high viable and innovative way to generate electronic devices: organic/flexible/printed electronics. This emerging research field enables novel, thin, lightweight and cost-efficient electronic systems. Current market drivers are organic photovoltaics [1,2], flexible batteries [3,4], electro-optic devices [5-7], OLED displays, logic and memory components – including field effect transistors (FETs) and organic thin film transistors (OTFTs) [8-12], sensor arrays [13-17] and radio frequency identification (RFID) tags [18,19]. Even though performance, yield nor reliability are as high as the achieved in silicon foundries, printed electronics technologies are improving on a daily basis and nowadays it is possible to make circuits that work properly on this kind of substrates. Currently, printed electronics work mainly with PMOS transistors due to its fabrications simplicity and traditionally higher conductivity of p-type organic semiconductor material compared with n-type. Consequently, the logic family used for this kind of logic is pseudo-PMOS, similar to old pseudo-NMOS style, but using PMOS transistors instead of NMOS. Logic gates following the pseudo PMOS style will have a pull-down PMOS transistor acting as a discharge resistor, while the pull-up is composed of a switch network that implements the logic of the gate. The pull-up switch network is an association of PMOS transistors controlled by the inputs. Fig. 1 presents a schematic comparing pseudo-NMOS (Fig 1.a), CMOS (Fig 1.b), and pseudo-PMOS (Fig 1.c). As it can be observed, pseudo-PMOS and pseudo- NMOS are quite similar, as these logic styles substitute one of the logic planes used in the CMOS style by a single depletion transistor that works as an electric load, though it can also be grounded or biased to -V SS . Organic transistors are being modelled using different approaches being one of the most popular and used in our work the Unified Model and Extraction Method (UMEM) [21,22] that shows the difference to the ideal MOS transistor behavior through a reduced set of parameters (mainly through gamma). (a) (b) (c) Fig. 1. Different logic styles: (a) Pseudo-NMOS, (b) CMOS and (c) pseudo-PMOS (depicted with 3 different loads).