International Journal of Engineering and Technical Research (IJETR) ISSN: 2321-0869, Volume-3, Issue-2, February 2015 61 www.erpublication.org Abstract— Over the last two decades, fixed coefficient FIR filters were generally optimized by minimizing the number of adders required to implement the multiplier block in the transposed direct form filter structure. In this paper, an optimization method for the structural adders in the transposed tapped delay line is proposed. Although additional registers are required, an optimal trade-off can be made such that the overall combinational logic is reduced. For a majority of taps, the delay through the structural adder is shortened except for the last tap. The one full adder delay increase for the last optimized tap is tolerable as it does not fall in the critical path in most cases. The criterion for which area reduction up to 4.5% to 9.5% and power reduction up to 10% to 30% for the structural adder block of three benchmarks filters is estimated theoretically. The saving is more prominent as the number of taps grows. The criterion for which reduction in number LUTs, number of bonded IOBs, & number of slices are derived. Actual synthesis results are obtained by Xilinx design ISE suite 14.3 (Sparten 3E family and device-XC3S100) & Cadence RTL compiler with 0.18μm TSMC CMOS libraries. Index Terms— FIR filter, Normal structural adder, proposed structural adder reduction, Xilinx design ISE suite 14.3 (Sparten 3E family and device-XC3S100) and Cadence RTL compiler with, 0.18μm TSMC CMOS libraries, Area & Power reduction. I. INTRODUCTION The inherit stability makes FIR filters a preferred choice in digital signal processing. As wireless technology advances, FIR filters with shorter transition bands, more stringent stopband attenuation requirement and higher sampling rate, are in great demand. To achieve these goals, ASIC implementation is necessary. The Transposed Direct Form (TDF) structure is preferred over direct form structure for higher order ASIC filters due to its shorter critical path delay. In the direct form structure, the input is delayed before the coefficient multiplication and the register length of each tap is fixed by the input bit width. In the TDF structure, the partial sums generated by the outputs of the coefficient multiplier, are delayed. Thus, the lengths of the registers increase monotonically along the taps to hold the correct precision of the partial sums. Consequently, the number of registers needed for the TDF structure is larger than that for the direct form. Fig. 1 shows a generic TDF fixed coefficient FIR filter. For long filters, the shorter critical path of the TDF is more significant than the costs of the registers. Manuscript received February 06, 2015. Raval Jay Manoj, M.Tech, SENSE Department, VIT University, Tamilnadu, India. S. Umadevi, SENSE Department, VIT University, Tamilnadu, India. Fig. 1 Transposed direct form FIR Filter. For fixed coefficient FIR filters, the bit widths of the input and all coefficients are known. This enables the bit width of the coefficient multiplier to be determined from its dynamic range. As the partial sums are delayed before they are added with the coefficient multiplier outputs in the structural adders, the bit widths of the structural adders increase monotonically from the first structural adder towards the output. Careful analysis revealed that for most filters, the bit width of the adder increases only from coefficient N−1 to about N/2, after which the bit width stays relatively constant and increases by no more than two bits. As the bit width of the coefficient multiplier output reduces towards the last tap, longer sign extension is required for these structural adders. This paper proposes an addition scheme to reduce the bit widths of these structural adders so that the total combinational logic is reduced at the expense of some register overhead. To determine if the area reduction is able to offset the overheads of additional adders and registers, a lower bound for the difference between the adder bit width and the coefficient multiplier output bit width is established analytically. II. PROPOSED STRUCTURAL ADDER OPTIMIZATION The fundamental concept of our proposed method can be illustrated by an example in decimal. Let {610,−274, 2, 258} be a set of coefficient multiplier outputs to be accumulated to a large partial sum 1234567 by the structural adders in a tapped delay line. A downright approach is to add one number at a time from the set of smaller integers to the large integer. Alternatively, the integers in the set are summed and then added to the large integer. The latter accumulation scheme, when implemented in hardware, requires the large integer and the smaller integers to be stored at each tap. This incurs a large register overhead, which can be reduced if the large number is split into two smaller integers as shown in Fig. 2. Structural adders reduction in fixed coefficient transposed direct form FIR filters Raval Jay Manoj, S. Umadevi