ISSN 2394-3777 (Print) ISSN 2394-3785 (Online) Available online at www.ijartet.com International Journal of Advanced Research Trends in Engineering and Technology (IJARTET) Vol. 2, Issue 4, January 2015 All Rights Reserved © 2015 IJARTET 142 A Reliable Process-Sensitive Tolerant Hybrid Sense Ultra Power SRAM Amplifier Thaiyai Nayagi 1 , A.P. Prabakaran 2 PG Student, A.V.C College of Engineering, Nagapattinam, India 1, 2 Abstract: — Power consumption has become a critical design concern for many VLSI systems. In this proposed system we use Sense amplifiers are one of the very important peripheral components of CMOS memories. In a Hybrid Sense amplifier both current and voltage sensing techniques are used which makes it a better selection than a conventional current or voltage sense amplifiers. To increase the memory density, bit cells used reduce the area. Power consumption and speed is the important issue to minimize the power value by using cell read and stability value. This paper is also investigating the read static noise margin, write noise margin and read retention voltage. Tanner EDA tool is also used to observe the schematic solution. This method will decrease the power consumption and increase the stability of the SRAM cell. Keywords: SRAM, Power gating, Voltage Sense Amplifier (VSA), Current Sense Amplifier (CSA), Dynamic Stability. I. INTRODUCTION In this paper we introduce some design techniques to reduce the power consumption and increase the stability f the cell. Each cell contains some transistors. Existing method we use 6T SRAM cell. Stability of the 6T SRAM cell is poor. Measuring the cell current by change cell structure. It will damage the circuit and reduce the stability and increase the losses. But in this method we accurately estimate the cell stability of the SRAM cell without modifying the cell structure. Existing system 32nm devices are used. The estimation results focused on the random manner. It will not display the final result. Random mismatches are occurs in the wafer. As the temperature is increases stability of the read mode and sleep mode deceases. In the proposed method we use the Sense amplifiers are one of the most essential circuits in the periphery of CMOS memories. The performance of sense amplifier affects both memory access time and overall memory power dissipation. CMOS memories are required to increase speed, improve capacity and maintain low power dissipation. These goals are conflicting when it comes to sense amplifier design. In an integrated circuit a memory is attached to number of peripherals which would use the contents of the memory, but the potential developed at the output nodes of the memory (6T SRAM) is too low to drive the peripheral circuitry, hence the need of a sense amplifier comes into picture. It senses a low signal and amplifies it to appropriate level. But most of the techniques are not directly applied to the SRAM cell. But this paper estimates the read and writes stability. II. BACKGROUND A. Static Noise Margin Read static and write noise margin are the extended definitions of the SNM. These two terms are defined as the, maximum tolerable noise injected onto the cell. B. Read Retention Voltage Supply read retention voltage is highly correlated. This technique can be used to extracts the cell read stability without changing the cell structure.6T SRAM cell read stability requires to sweeping the internal nodes in order to obtain the voltage transfer curvatures. Large are used to choose the Supply Read Retention Voltage. 6T SRAM cell structure we use two CMOS inverter. Word line used to control the circuit. 6T circuit are contains Pull up and Pull Down transistors. Other two transistors are called as the access transistors. Voltage division between the access transistor and driver transistor read stability to be low during the read operation. Leakage current is flows through the NMOS transistor. It will increase the source to supply voltage. More than one transistor is off means the path between the supply voltage to ground is equal.