INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS www.ijrcar.com Vol.3 Issue.5, Pg.: 13-19 May 2015 B. Venkata Sreecharan & C. Venkata Sudhakar Page 13 INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS ISSN 2320-7345 EFFICIENT MULTIOUTPUT CARRY LOOK-AHEAD ADDERS B. Venkata Sreecharan 1 , C. Venkata Sudhakar 2 1 M.TECH (VLSI DESIGN) Deportment of ECE SVNE, Tirupathi, boyapati.brothers@gmail.com 2 ASSISTANT PROFESSOR Deportment of ECE SVNE, Tirupathi, sudhakar.chowdam@gmail.com Abstract: - Addition is the fundamental operation for any VLSI processors or Digital Signal Processing (DSP). In this paper we present an efficient implementation of a 16-bit Manchester carry chain (MCC) adder using an enhanced multiple output domino logic. In adder circuits the main drawback is propagation delay and to overcome this drawback using domino logic. In this paper 4-bit, 8-bit and 16-bit adders are been designed and power, delay and area are measured using TANNER tool, and then compared with the conventional adder. The experimental results reveal that the proposed adders achieve delay, power and area reductions for Multi bit addition. Keywords: Carry look-ahead adder, domino logic, Manchester carry chain, High Performance, delay, TANNER tool. I. Introduction In VLSI the one of the basic components are adders for an ALU and there are „n‟ number of adders each with their own advantages and disadvantages. When two numbers are to be added and if each of them is of „n‟ bits then we can add them in two different ways serial and parallel. High-speed adder architectures include the Ripple-Carry Adder (RCA), Carry-Select Adders (CSLA), Carry-Skip Adders (CSA), Carry Look-Ahead (CLA) adders [1], Conditional sum adders and combinations of these high speed adders based on the carry look-ahead adders principle. Ripple-Carry Adder: A Ripple-Carry Adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascaded with the carry output from each full adder connected to the carry input of the next full adder in the chain. Fig.1 shows the interconnection of four full adder (FA) circuits to provide a 4-bit ripple carry adder. Notice from Fig.1 that the input is from the right side because the first cell traditionally represents the least significant bit (LSB). Bits a 0 and b 0 represent the least significant bits of the numbers to be added. The sum output is represented by the bits s 0 to s 3.