An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization Sherif M. Saif, Hazem M. Abbas Member, IEEE, and Salwa M. Nassar Member, IEEE Abstract— This paper presents a Field Programmable Gate Array (FPGA) implementation for a Competitive Hopfield Neu- ral Network (CHNN) to be used in image histogram equalization (HE). This algorithm is so computationally expensive that a viable hardware implementation is appealing provided that an efficient algorithm-to-architecture mapping can be achieved. The Xilinx Virtex-E was used for the hardware realization. An efficient use of the chip is outlined in the results. I. I NTRODUCTION Image processing algorithms in general are computa- tionally expensive. They become more time consuming, as the amount of input data increases. Implementation of image processing algorithms by using custom hardware, gives superior performance, compared to general purpose microprocessors, because the application specific hardware is configured to meet the computational requirements of the implemented algorithm. By using custom hardware, a real-time performance can be achieved. This has encouraged several attempts for implementation of image processing algorithms on custom hardware such as Walsh-Hadamard transform [1], Discrete Cosine Transform (DCT) [2] and an image encryption algorithm [3]. The aim of this work is to design a real-time reusable image enhancement architecture for video signals, based on a statistical processing of the video sequence. The histogram of an image represents the distribution of the pixels in the image over the available gray-level scale. When the gray- level values of the pixels are too close together, modification of the image histogram enhances its contrast. Histogram equalization attempts to match the original histogram to a histogram in which the bins are equally distributed, and therefore produces a histogram with a uniform or constant distribution in which each gray-level bin contains the same number of pixels. Variants to Histogram Equalization were presented in the literature to achieve better performance and to overcome some problems in the original technique [4][5][6][7]. Hopfield Neural networks (HNN) can be set up to solve optimization problems [8] in a very efficient way that achieved results which compete effectively and even out- perform other popular heuristics. CHNN was employed in [9] to solve the optimization problem introduced in the for- mulation of the regional HE. CHNN was used to give better equalization results by segmenting the image into regions and Sherif M. Saif and Hazem M. Abbas are with Mentor Graphics Corp., 51 Beirut St., Cairo 11341, Egypt (email: (sherif saif,hazem abbas)@mentor.com). Salwa M. Nassar is with Electronic Research Institute, Giza, Egypt. equalizing each region alone. However, if neural networks are to be applied routinely to practical problems, then the execution time must be reduced. There are a number of ways to accelerate the execution of the network algorithms, ranging from the use of high-end parallel supercomputers, through to hardware implementations of the networks themselves using custom computing machines. An FPGA implementation of the basic HE was reported in [10] where a real-time video signal processing chip for video data enhancement was developed and a 46 MHz clock was achieved. In this paper, we propose an FPGA implementation for the CHNN algorithm used in regional HE. The VHDL hardware description language has been used in order to model, simulate and bench-mark the designed circuit to implement CHNN for the histogram equalization technique. The paper is organized as follows. In section II the HE algorithm is explained. Section III describes CHNN. The hardware formulation and implementation of CHNN for HE is presented in Section IV. The analysis and results of the proposed design are presented in section V. Section VI presents the conclusions. II. HISTOGRAM EQUALIZATION Images can be transformed into new ones using precalcu- lated and stored tables. In addition, it is sometimes advanta- geous to construct a transfer function for a specific image. The most popular of these methods is called histogram equalization [11]. From the standpoint of efficiently using the available gray levels on the display, some gray scale values are underutilized. It might be better to spread out the displayed gray levels in the peak areas selectively, compressing them in the valleys so that the same number of pixels in the display shows each of the possible gray levels. This is called histogram equalization. The transfer function is simply the original gray-level histogram of the image, replotted as a cumulative plot. After equalization the cumulative plot is a straight line [12]. For each gray level j in the original image (and its histogram), the new assigned value k is calculated as k = j  i=0 N i T (1) where the sum counts the number of pixels in the image (by integrating the histogram) with gray value equal to or less that j , N i is the number of pixels having a gray value i, 0-7803-9490-9/06/$20.00/©2006 IEEE 2006 International Joint Conference on Neural Networks Sheraton Vancouver Wall Centre Hotel, Vancouver, BC, Canada July 16-21, 2006 5122