Border Trap Characterization in Metal-Oxide-Graphene Capacitors with Hf0 2 Dielectrics Mona A. Ebrish, David A. Deen and Steven J. Koester* University of Minnesota-Twin Cities, 200 Union St. SE, Minneapolis, MN 55455 *Ph: (612) 625-1316, FAX: (612) 625-4583, Email: skoester@umn.edu Introduction: Graphene is a promising material for electronic applications due to its high mobility, low density of states, and monolayer thickness [1]. In order to realize practical devices [2], the interface properties between graphene and high-K dielectrics must be understood. However, due to the different nature of the bonding at the graphene 1 dielectric interface, techniques developed to study the Si/Si0 2 interface cannot be utilized. Some interface-state extraction methods have been reported for graphene [3-5], though, to our knowledge; there have been no attempts to understand the trapping mechanisms that lead to the frequency- and temperature-dependent capacitance-voltage (C-V) characteristics that are observed experimentally. In this work, a border trap model is employed to explain the observed frequency-dependent capacitance characteristics of metal-oxide-graphene (MOG) capacitors. Specifically, we have analyzed single-layer graphene capacitors with local-metal gates and Hf0 2 dielectrics, a geometry which allows scaled dielectrics to be analyzed, and also avoids non-idealities associated with dielectric nucleation on graphene. In addition, this geometry allows us to compare our results with metal-insulator-metal (MIM) capacitors that utilize the same dielectric, thus allowing us to differentiate bulk Hf0 2 effects from those associated with the grapheneldielectric interface. In this work, we compare the C-V characteristics of MOG capacitors with Hf0 2 dielectrics. Frequency- dependent capacitance measurements indicate border-trap-like behavior at high temperatures and voltages, with trap density of r-.J 1-2 x 10 18 cm- 3/eV, results similar to those obtained on MIM capacitors. At lower temperatures, the trapping mechanism freezes out, suggesting an interfacial layer between the graphene and Hf0 2 Device Fabrication: The fabrication sequence [6] for the capacitors is shown in Fig. 1(a)-(d). Briefly, the quasi- planar gate electrodes consisting of Ti/Pd (10/40 nm) were embedded into Si0 2 by dry etching. Next, Hf0 2 was deposited by atomic-layer deposition (ALD) at 300°C, followed by annealing in an Ar ambient at 400°C for 5 minutes. Single-layer CVD graphene grown on a Cu foil was then transferred onto the sample using a standard aqueous transfer process. After patterning and etching the graphene in an O 2 plasma, Ti/Pd/Au (1.5145/100 nm) Ohmic contacts were patterned and lifted off. The MOG capacitors were arranged in a multi-finger geometry to reduce parasitic series resistance as shown in Fig. 2. Metal-insulator-metal (MIM) capacitors were also fabricated where the Ohmic metal was utilized as the top electrode. The samples were tested in vacuum (r-.J 10- 6 Torr) at temperatures ranging from 4.2 K to 380 K. AC impedance measurements were performed using a 50 mV oscillator voltage at frequencies from 1 kHz to 1 MHz and the capacitance was extracted assuming a series (Cs-R s) equivalent circuit. Results: The C-V characteristics for an MOG capacitor with target Hf0 2 thickness of 6.8 nm are shown in Fig. 3 at three different frequencies and two temperatures (T = 4.2 K and 380 K), while the full temperature dependence is shown in Fig. 4. Strong frequency dispersion is observed at higher temperatures. The absence of frequency dispersion at T = 4.2 K is an indication of trap freeze out, and therefore this characteristic was used to fit a value for the residual temperature, To, (Fig. 5(a)) which is a measure of the strength of the random potential fluctuations [6]. An area scaling term was also introduced to indicate partial delamination of the graphene. A comparison of the capacitance per unit area of the MOG and MIM capacitors (Fig. 5(c)) shows that the equivalent oxide thickness (EOT) is substantially higher for the MOG capacitors vs. the MIMs, a trend that is observed consistently on multiple samples. To explore the nature of the graphene- Hf0 2 interface, the capacitance vs. frequency characteristics were analyzed. Here, the excess measured capacitance (relative to the theoretical model) was plotted vs. frequency, and a linear dependence of vs. In(/) was observed. At high temperature and high bias (Fig. 6), a relatively temperature-independent slope was observed, a trend consistent with border traps. Near the Dirac point (Fig. 7), however, a temperature-dependent slope was observed, suggesting an additional mechanism. These same measurements were performed on the MIM capacitors (Fig. 8) and the results show linear C vs. In(/) for all temperatures and biases. The border trap density has been extracted from the slope of the C vs. In(/) curves using a simple first-order approximation (Fig. 10). The extracted values of N bt vs. V g for both the MOG and MIM capacitors are shown in Fig. 9. The border trap density for the MIM capacitors is on the order of 1-2 x 10 18 cm- 3/eV, consistent with prior studies on Hf0 2 [7-8]. The agreement between the high-temperature N bt values between the MOG and MIM capacitors also suggests that the same Hf0 2 border traps are the primary cause of dispersion in the MOG capacitors. However, the freeze-out behavior in the MOG capacitors could be the result of an interfacial layer between the graphene and Hf0 2 , a conclusion that is supported by the discrepancy between the EOT values shown in Fig. 5(c). The parallel conductance to the broader trap capacitance (Fig. 11(a)-(b)) shows an activated behavior for the MOG samples, with similar values between the MIM and MOG conductance at room temperature, further evidence of an interfacial layer on the MOG samples. Conclusion: Dielectric trapping in MOG capacitors with Hf0 2 dielectrics has been studied. Border traps dominate at high temperature, while the freeze out of this trapping mechanism suggests the existence of an interfacial layer. 978-1-4799-0814-1/13/$31.00 ©2013 IEEE 37