International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.2, April 2014 DOI : 10.5121/vlsic.2014.5202 11           Vaishali Dhare and Dr. Usha Mehta Institute of Technology, Nirma University, Ahmedabad, Gujarat, India ABSTRACT To generate test patterns for the complex VLSI designs, an efficient and simple technique is required. This paper present the development of combinational ATPG based on FAN algorithm, testability measures and fault equivalence. The prime aspect of this work is to develop the ATPG algorithm with less number of faults and testability measures. The proposed ATPG algorithm is simple and can be used as an open source for academicians. Analysis on ISCAS 85 circuit along with some basic combinational circuits are present for stuck-at faults. KEYWORDS ATPG, fault equivalence, testability measures, ISCAS, FAN. 1. INTRODUCTION Automatic Test Pattern Generation (ATPG) is the process of generating patterns to test a circuit. A significant amount of research has been done in the area of gate-level combinational ATPG using the stuck-at-fault model. As the numbers of transistors are increasing on chip, it is becoming difficult to generate the test vectors to test all faults. The objective of testing is filtering defective chips from manufactured ones to reduce the fraction of defective parts those are erroneously sold to customers as defect-free parts [1]. The commercial ATPG tools are available in the market like FastScan by Mentor Graphics, TetraMAX by Synopsys. The cost of these ATPGs is high also it is not possible to analyze the algorithm of it. Our aim was to develop an open source advanced ATPG which would be freely available to generate the test patterns and to analyze the concept of controllability, observability and fault equivalence. The single stuck-at- fault model has been widely accepted as a standard target model to generate a set of test patterns to detect all the stuck faults in the circuit [2]. In this paper single stuck at fault model is considered. If we consider single stuck at fault (Stuck at 0 and Stuck at 1) then the number of faults and test vectors are 2n, where n is number of nets. Size of test vector becomes large for large combinational circuits. The bandwidth requirement of ATE and test time may be more in this case [3]. No doubt that test vector compression methods are available but prior to it fault reduction is possible using fault equivalence method. The reduced fault set concept using fault equivalence is described and developed in [4]. ATPG (Automatic Test Pattern Generation) should be guided by the testability measures to choose a decision during justification and propagation. These measures serve as heuristics and represent the relative difficulty of justifying a gate value to a control input or propagating a fault effect to an observe point. The testability measures, controllability and observability is described and developed in [5].