Verification & Design Techniques Used in a Graduate Level VHDL Course Prof. Swati Agrawal Associate Professor, Department of Electronics & Telecommunication Bhilai Institute of Technology, Durg, India International Journal of Research in Electronics & Communication Technology Volume 3, Issue 1, January-February, 2015, pp. 01-06 ISSN Online: 2347-6109 Print: 2348-0017, DOA : 07022015 © IASTER 2014, www.iaster.com ABSTRACT Use of the VHSIC Hardware Description Language (VHDL) has become very important to the simulation and implementation of digital systems in both industry and educational settings. Al-though VHDL is a powerful language with many capabilities, it has downfalls when considering the difficulty in learning the language as well as its limited capabilities for transitioning a design from initial concept to design entry and verification stages. This paper discusses techniques used to teach the VHDL design methodology to graduate students, as well as methods used to go through a complete design cycle from initial concept to final implementation. VHDL design techniques were developed using various projects and homework assignments and different approaches to implementing the same function allowed direct comparisons of the speed and size of the designs. Different processes for taking a design from initial concept through chip implementation were discussed, and one example of the process is discussed here. This paper describes the implementation of full adder using VHDL technology which meets less complexity requirement ,it also shows how efficiently digital system i.e. Full Adder is implemented up to layout level results shows technological map RTL view, chip floor plan, chip layout ,output waveforms showing voltage Vs time relations and verification of truth table . 1. INTRODUCTION The use of Hardware Description Languages (HDL's) has been steadily increasing as digital designs become larger and more complex. Previously used methods such as schematic capture have not been as well suited to design re-use and rapid prototyping of large chip designs. Although not new, HDL's have recently become popular with the widespread use of two similar but distinct languages. The older of these languages, VHDL (VHSIC Hardware Description Language)[1], is heavily used by U.S. defense agencies and large corporations, as well as a majority of European companies. VHDL was first adopted as language standard in 1987, with a major revision occurring in 1993. The other major HDL currently in use is Verilog[2], which is more common among smaller companies and corporations with fewer ties to the military. While both languages are very powerful and can be used to obtain the same results, the VHDL syntax is more complex than Verilog. This paper describes the learning methods used in teaching an upper level course on VHDL. Students are expected to use their new knowledge to implement designs in VHDL.