International Journal of Scientific and Research Publications, Volume 5, Issue 6, June 2015 1 ISSN 2250-3153 www.ijsrp.org SDRAM Controller Based Vedic Multiplier in DWT Processor for Video Processing Prof Pramod Kumar Naik * , Prof Gurusandesh M * , Prof Arun S Tigadi ** , Dr.Hansraj Guhilot *** * Department of Electronics & Communication Engineering, VCET, Puttur, Karnataka, India ** Department of Electronics & Communications, KLE DR. M.S.S CET, Belgaum, Karnataka, India *** Principal K.C.College of Engineering & Management Studies and Research, Thane, Maharashtra, India Abstract- Real time video processing has been the subject of interest for research work in last decade. Image and video processing technique are computationally demanding for various applications in various domains. Due to overwhelming demand we have focused on designing and implementing this new architecture which is effective. This paper we have focused on designing a DWT VEDIC processor which has a special SDRAM controller which takes care of this real time video processing. The design here is focused on real time DWT video compression and implementing the design on a Spartan 6 Altys FPGA board. Real time video applications have been implemented in the architecture with various results are projected to demonstrate its applicability and flexibility. Index Terms- DWT, DCT, SDRAM. I. INTRODUCTION iscrete wavelet transform (DWT) decomposes images into multiple sub bands of low and high frequency component. This encoding of sub band components leads to compression of image and video .Image compression finds application in every discipline such as entertainment, medical, defence, industrial and commercial sectors. Thus the core of compression unit is DWT.DWT has lot of computational mathematical operations which are very intensive operations which consumes lot of time and power .Our focus is on design of SDRAM controller which controls data movement in DWT computation and to increase the performance of DWT Processor we are designing and implementing a 16*16 vedic multiplier in the DWT processing unit. This architecture has greatly reduce the power consumption of the circuit and at the same time increase the speed of operation of processing unit. The rapid increase in packing density, clocking frequency and computational power of an embedded system in general has inevitably resulted in rise in power consumption .For many years to come, miniaturization of size of devices together with the search of various architectures for low power and voltage requirement will continue. The work explores the new DWT architecture with Vedic multipliers incorporated in designing the hardware and determining its power consumption. II. SYNCHRONOUS CONTROLLER The usual memory hierarchy of a FPGA includes the data path, Main Memory Controller (MMC) and Local Memory Controller (LMC) as shown in the below figure1.The MMC will control the SDRAM (Synchronous Dynamic Random Access Memory) and generates the burst signals for the remaining units of the device. The LMC controls the data path and waits for the burst signals from the MMC. The main aim of our paper is to design Synchronous Ram Controller which will help to improve the performance matrix of the Vedic multiplier which will act as one of the component inside the DWT processor. Fig 3.1 Architecture of MAC Unit in a processor. III. MULTIPLY AND ACCUMULATE UNIT In most of the digital signal processing units the critical operations involved are comprised of many multiplications and accumulations. There for the key focus is to increase the speed of any digital signal processing unit. In this regard our focus is to use vedic mathematics and design a high speed and high through put Multiplier-Accumulator Unit. These days computers contains dedicated video graphics unit similarly computers may contain dedicated MAC unit. The generalised structure of MAC unit is shown in the figure 3.1 below. The MAC unit consists of a multiplier implemented in combinational logic followed by an adder and an accumulator registers which stores when clocked. The output of the register is fed back to one input of the adder, so that on each clock, the output of the multiplier is added to the register. Combinational multipliers require a large amount of logic, but can compute a product much more quickly than the shift and add based multiplier. D