High Performance Scalable On-Chip Interconnects: Unleashing System Performance Mohammad AsifKhan, Javed Ahmed, Ahmed Waqas Department ofComputer cience, Sukkur Institute ofBusiness Administration Airport Roa, Suur Sind, Pakistan asif.khan@iba-suk.edu.pk, javed@iba-suk.edu.pk, ahmad.waqas@iba-suk.edu.pk Asrat- There is aways demand for high performance single chip microprocessor. In this regard microprocessor's manufactures have wored hard and have gone through diferent techniques like increasing its clock speed, cache sie, cores and hyper threading. But for past fw years the designer have realied that all these techniques are insigniicant until microprocessor have fast interconnect, which can provide fast access to memory, its cores and other 110 devices. FSB (Front Side Bus) was used in microprocessos which was shared pathway for communication of microprocessos wth other devices. FSB with shared nature has a great amount of contention for its access, which introduced performance bottle neck in this architecture. To over come the bottle necks ofFSB both MD and Intel have introduced their proprietary standards HyperTransport and QuicPath interconnect respectively. Both of these interconnects are designed by keeping in view low latency, high bandwidth, scalable point-to-point interconnect, which can cope with the high performance needs of On-Chip microprocessor. These two interconnects have remarkably greater performance than traditional FSB and are well shaped for the future generations of microprocessos. Kwor-- QuicPath, HyperTransport,Front Side Bus (FSB), On-Chip Interconnect, Scalable Interconnet I. I NTRODUCTION For past ten yers the microprocessor mnuacturers have worked on diferent techniques to develop single chip microprocessrs with high performnce. To chieve this goal desiners have worked on diferent asects like increasing processor's clock speed, increasing cache size, increasing number of core on a single chip of rocessor nd processor bus. Increasing the bus performnce of processr is one of the most importnt aspect which cn lead processor towrds high performnce, ecuse bus is the nly communiction link through which microprocessor communictes with memory, hrd disk nd other /O devices [4].Having processor tht is good in all other aspects but is with ineicient microrocessor bus would lead to a sitution where processr will execute its instructions quickly, but bus will process them slowly as result of this processor will wit for the response, nd microrocessor's cycles will be wasted. Hence microprocessor bus/Intrconnect has ret impact over its performnce [1]. In strt mnuacturers used FSB (Front Side Bus) as a microprocessor's bus, Pentium Pro was the irst 978-1-61284-941-6/11/$26.00 >2011 IEEE 21 microrocessor rom Intel Corportion to use it [14].FSB provides a shred pthway between processor nd other devices. Intel continued to use FSB in its processors till irst genertion of Core2 processor series. Intel was able to cntinue with FSB for long time becuse Intel brought very good innovtions into the rchitecture of FSB to increase its performnce by reducing ltency nd increasing its bndwidth. Intel increased FSB's performnce by increasing FSB trnsfer per cycle to 2X nd then to 4X which is also called quad pumped FSB. With this Intel chnged FSB rchitecture to DIB (Dual Independent Bus) nd then to DHSI (Dedicted hih speed Intercnnet) [1]. AMD also used FSB with its microrocessors nd uses EV6 technology to boost bus to 2X dta trnsfer er clock cycle [7]. AD relized ht FSB desin is no mre sclable nd it is useul to deelp new solution nd desined a new microrocessr itrcnnt for its next gntim microrocessors. AD introduced HyerTrnsport Technoloy to replce FSB in yer 2001[13]. Atr replacig FSB with HyperTrnsprt tchnoloy intrconnet AD has made god innovtins in its rchitecture y rinig diernt versims of HyperTrnsport intrconnet versions L, 2.0 nd 3.0. Intel brought some very good innovtions to FSB's rchitecture but they also realized the bttleneck of FSB as its erfrmnce was not scaling well to support its net genertion microrchitectures of microprocessors. Intel in 2008 introduced QuickPth interconnect in its microrchitectures Nehalem nd Tukwila [3]. QuickPth is low ltency, high bndwidth, scalble point-to-point intercnnect. his Interconnect is well equiped with fetures to support Intel's next genertion of microrocessors [3]. In this paper we describe importnce of interconnect or bus for rocessor performnce nd provided survey of vrious approaches used by diferent processor mnufacturers. In section II of this paper FSB is described riely, ater having concept of FSB nd its diferent vritions a brief description about Intel's Quick Pth rchitecture is given in section III. AMD's HyperTrnsport interconnect is discussed in section IV. At the end oth Intel Quick Pth nd AMD HyperTrnsport technology re compred to conclude which one is the best for meeting the uture demnds of low ltency, high bndwidth nd scalble interconnet for ture gnertions of microprocessrs.